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1.发明授权公开(公告)号：US09481940B2
公开(公告)日：2016-11-01
申请号：US14315390
申请日：2014-06-26
发明人： Charles L. Arvin , Jürg Stahl
CPC分类号： C25D3/56 , C23F13/005 , C25D3/30 , C25D3/46 , C25D3/60 , C25D3/64 , C25D17/10 , C25D21/00 , C25D21/12
摘要： Disclosed are an electrodeposition system and method with an anode assembly comprising a capacitor comprising a first conductive plate (i.e., an anode) with a frontside having a surface exposed to a plating solution, a second conductive plate on a backside of the first conductive plate, and a dielectric layer between the two conductive plates. During a non-plating mode, a power source, having positive and negative terminals connected to the first and second conductive plates, respectively, is turned on, thereby polarizing the first conductive plate (i.e., the anode) relative to the second conductive plate to prevent degradation of the anode and/or plating solution. During an active plating mode, another power source, having positive and negative terminals connected to the first conductive plate (i.e., the anode) and a cathode, respectively, is turned on, thereby polarizing the anode relative to the cathode in order to deposit a plated layer on a workpiece.
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2.发明申请公开(公告)号：US20150376808A1
公开(公告)日：2015-12-31
申请号：US14315390
申请日：2014-06-26
发明人： Charles L. Arvin , Jürg Stahl
CPC分类号： C25D3/56 , C23F13/005 , C25D3/30 , C25D3/46 , C25D3/60 , C25D3/64 , C25D17/10 , C25D21/00 , C25D21/12
摘要： Disclosed are an electrodeposition system and method with an anode assembly comprising a capacitor comprising a first conductive plate (i.e., an anode) with a frontside having a surface exposed to a plating solution, a second conductive plate on a backside of the first conductive plate, and a dielectric layer between the two conductive plates. During a non-plating mode, a power source, having positive and negative terminals connected to the first and second conductive plates, respectively, is turned on, thereby polarizing the first conductive plate (i.e., the anode) relative to the second conductive plate to prevent degradation of the anode and/or plating solution. During an active plating mode, another power source, having positive and negative terminals connected to the first conductive plate (i.e., the anode) and a cathode, respectively, is turned on, thereby polarizing the anode relative to the cathode in order to deposit a plated layer on a workpiece.
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3.发明授权公开(公告)号：US10156019B2
公开(公告)日：2018-12-18
申请号：US15802619
申请日：2017-11-03
发明人： Charles L. Arvin , Jürg Stahl
IPC分类号： C25D3/56 , C25D21/00 , C23F13/00 , C25D3/30 , C25D3/46 , C25D21/12 , C25D3/60 , C25D3/64 , C25D17/10
摘要： Disclosed are an electrodeposition system and method with an anode assembly comprising a capacitor comprising a first conductive plate (i.e., an anode) with a frontside having a surface exposed to a plating solution, a second conductive plate on a backside of the first conductive plate, and a dielectric layer between the two conductive plates. During a non-plating mode, a power source, having positive and negative terminals connected to the first and second conductive plates, respectively, is turned on, thereby polarizing the first conductive plate (i.e., the anode) relative to the second conductive plate to prevent degradation of the anode and/or plating solution. During an active plating mode, another power source, having positive and negative terminals connected to the first conductive plate (i.e., the anode) and a cathode, respectively, is turned on, thereby polarizing the anode relative to the cathode in order to deposit a plated layer on a workpiece.
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4.发明申请公开(公告)号：US20180051385A1
公开(公告)日：2018-02-22
申请号：US15802619
申请日：2017-11-03
发明人： Charles L. Arvin , Jürg Stahl
IPC分类号： C25D3/56 , C25D21/12 , C25D21/00 , C25D3/64 , C23F13/00 , C25D3/60 , C25D3/46 , C25D3/30 , C25D17/10
CPC分类号： C25D3/56 , C23F13/005 , C25D3/30 , C25D3/46 , C25D3/60 , C25D3/64 , C25D17/10 , C25D21/00 , C25D21/12
摘要： Disclosed are an electrodeposition system and method with an anode assembly comprising a capacitor comprising a first conductive plate (i.e., an anode) with a frontside having a surface exposed to a plating solution, a second conductive plate on a backside of the first conductive plate, and a dielectric layer between the two conductive plates. During a non-plating mode, a power source, having positive and negative terminals connected to the first and second conductive plates, respectively, is turned on, thereby polarizing the first conductive plate (i.e., the anode) relative to the second conductive plate to prevent degradation of the anode and/or plating solution. During an active plating mode, another power source, having positive and negative terminals connected to the first conductive plate (i.e., the anode) and a cathode, respectively, is turned on, thereby polarizing the anode relative to the cathode in order to deposit a plated layer on a workpiece.
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5.发明授权公开(公告)号：US09863051B2
公开(公告)日：2018-01-09
申请号：US14831252
申请日：2015-08-20
发明人： Charles L. Arvin , Jürg Stahl
IPC分类号： C25D3/56 , C25D21/00 , C23F13/00 , C25D3/30 , C25D3/46 , C25D21/12 , C25D3/60 , C25D3/64 , C25D17/10
CPC分类号： C25D3/56 , C23F13/005 , C25D3/30 , C25D3/46 , C25D3/60 , C25D3/64 , C25D17/10 , C25D21/00 , C25D21/12
摘要： Disclosed are an electrodeposition system and method with an anode assembly comprising a capacitor comprising a first conductive plate (i.e., an anode) with a frontside having a surface exposed to a plating solution, a second conductive plate on a backside of the first conductive plate, and a dielectric layer between the two conductive plates. During a non-plating mode, a power source, having positive and negative terminals connected to the first and second conductive plates, respectively, is turned on, thereby polarizing the first conductive plate (i.e., the anode) relative to the second conductive plate to prevent degradation of the anode and/or plating solution. During an active plating mode, another power source, having positive and negative terminals connected to the first conductive plate (i.e., the anode) and a cathode, respectively, is turned on, thereby polarizing the anode relative to the cathode in order to deposit a plated layer on a workpiece.
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6.发明申请ELECTRODEPOSITION SYSTEM AND METHOD INCORPORATING AN ANODE HAVING A BACK SIDE CAPACITIVE ELEMENT 有权包含背面电容元件的阳极的电沉积系统和方法公开(公告)号：US20150376812A1
公开(公告)日：2015-12-31
申请号：US14831252
申请日：2015-08-20
发明人： Charles L. Arvin , Jürg Stahl
CPC分类号： C25D3/56 , C23F13/005 , C25D3/30 , C25D3/46 , C25D3/60 , C25D3/64 , C25D17/10 , C25D21/00 , C25D21/12
摘要： Disclosed are an electrodeposition system and method with an anode assembly comprising a capacitor comprising a first conductive plate (i.e., an anode) with a frontside having a surface exposed to a plating solution, a second conductive plate on a backside of the first conductive plate, and a dielectric layer between the two conductive plates. During a non-plating mode, a power source, having positive and negative terminals connected to the first and second conductive plates, respectively, is turned on, thereby polarizing the first conductive plate (i.e., the anode) relative to the second conductive plate to prevent degradation of the anode and/or plating solution. During an active plating mode, another power source, having positive and negative terminals connected to the first conductive plate (i.e., the anode) and a cathode, respectively, is turned on, thereby polarizing the anode relative to the cathode in order to deposit a plated layer on a workpiece.
摘要翻译： 公开了一种具有阳极组件的电沉积系统和方法，阳极组件包括电容器，该电容器包括具有暴露于电镀溶液的表面的前侧的第一导电板（即，阳极），第一导电板的背面上的第二导电板， 以及两个导电板之间的介电层。 在非电镀模式期间，分别具有连接到第一和第二导电板的正端子和负极端子的电源被接通，从而使第一导电板（即，阳极）相对于第二导电板偏振到 防止阳极和/或电镀液的劣化。 在有源电镀模式期间，分别连接到第一导电板（即阳极）和阴极的正极端子和负极端子的另一个电源被接通，从而使阳极相对于阴极极化，以便沉积 工件上镀层。
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公开(公告)号：US11410894B2
公开(公告)日：2022-08-09
申请号：US16562583
申请日：2019-09-06
IPC分类号： H01L23/34 , H01L23/13 , H01L23/373 , H01L23/367 , G06F3/00 , H01L23/00 , H01L25/065
摘要： An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.
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公开(公告)号：US11168400B2
公开(公告)日：2021-11-09
申请号：US16014579
申请日：2018-06-21
摘要： At least one plating pen is brought into aligned relationship with at least one hole defined in a board. The pen includes a central retractable protrusion, a first shell surrounding the protrusion and defining a first annular channel therewith, and a second shell surrounding the first shell and defining a second annular channel therewith. The protrusion is lowered to block the hole and plating material is flowed down the first channel to a surface of the board and up into the second channel, to form an initial deposit on the board surface. The protrusion is raised to unblock the hole, and plating material is flowed down the first annular channel to side walls of the hole and up into the second annular channel, to deposit the material on the side walls of the hole.
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公开(公告)号：US11031373B2
公开(公告)日：2021-06-08
申请号：US16369532
申请日：2019-03-29
发明人： Charles L. Arvin , Bhupender Singh , Richard Francis Indyk , Steve Ostrander , Thomas Weiss , Mark Kapfhammer
IPC分类号： H01L25/065 , H01L23/00 , H01L23/522 , H01L23/532
摘要： A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.
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公开(公告)号：US10957650B2
公开(公告)日：2021-03-23
申请号：US16546912
申请日：2019-08-21
IPC分类号： H01L23/538 , H01L23/00 , H01L23/498 , H01L25/00 , H01L25/065
摘要： A module including a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate. The semiconductor devices each having first bonding pads having a first solder joined with the base substrate and the semiconductor devices each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads; the semiconductor devices positioned adjacent to each other such that the bridge support structure joins to both of the semiconductor devices by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads.
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