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公开(公告)号：US08669786B1
公开(公告)日：2014-03-11
申请号：US13707789
申请日：2012-12-07
发明人： Kai D. Feng , Jong-ru Guo , Trushil N. Shah , Ping-Chuan Wang , Zhijian Yang
IPC分类号： G01R25/00
摘要： A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.
摘要翻译： 时钟相移检测器电路可以包括接收第一和第二时钟信号的相位检测器，由此相位检测器基于第一和第二时钟信号之间的相位差产生相位信号。 第一积分器耦合到相位检测器，接收相位信号，并产生积分相位信号。 第二积分器接收第一时钟信号并产生积分的第一时钟信号。 比较器耦合到第一和第二积分器，由此比较器接收积分相位信号和集成的第一时钟信号。 然后，比较器可以产生控制信号，该控制信号基于积分相位信号和集成的第一时钟信号之间的幅度比较来检测第一和第二时钟信号的相位差与优化的相位差之间的变化。
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2.发明授权Calibration of sampling phase and aperature errors in multi-phase sampling systems 有权多相采样系统中采样相位和温度误差的校准公开(公告)号：US09369263B1
公开(公告)日：2016-06-14
申请号：US14788192
申请日：2015-06-30
发明人： Matthew B. Baecher , John F. Bulzacchelli , John F. Ewen , Gautam Gangasani , Mounir Meghelli, I , Matthew J. Paschal , Trushil N. Shah
CPC分类号： H04B17/21 , G01R25/00 , H03K5/1565 , H04L1/24
摘要： Method and apparatus to calibrate sampling phases of a multi-phase sampling system. The method includes on-chip generating a pristine phase reference pattern signal for use in generating at least one reference output signal from a data path; sampling, responsive to a clock signal, the at least one reference output signal to obtain samples; and modifying a phase of the clock signal to align the obtained samples to pattern edges of at least one reference output signal. Both symmetric and asymmetric duty cycle distortion are removed from the pristine phase reference pattern signal input to the data path. The effects of asymmetric distortion in the data path output signal upon the phase calibration are cancelled by periodically inverting the at least one reference output signal. The method adjusts a first phase sampling clock signal output of an electronic phase rotator device to provide an initial alignment setting against a first edge of the reference output signal; and then implements phase calibration logic to align a second phase sampling clock signal against a second edge.
摘要翻译： 校准多相采样系统采样相位的方法和装置。 该方法包括片上生成用于从数据路径生成至少一个参考输出信号的原始相位参考图形信号; 响应于时钟信号采样所述至少一个参考输出信号以获得采样; 以及修改所述时钟信号的相位以将所获得的样本对准至少一个参考输出信号的图形边缘。 从输入到数据通道的原始相位参考图形信号中去除对称和非对称占空比失真。 通过周期性地反转至少一个参考输出信号来消除相位校准时数据通路输出信号中的非对称失真的影响。 该方法调节电子相位旋转器装置的第一相位采样时钟信号输出以针对参考输出信号的第一边沿提供初始对准设置; 然后实施相位校准逻辑以将第二相位采样时钟信号与第二边沿对准。
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公开(公告)号：US09077319B2
公开(公告)日：2015-07-07
申请号：US14156795
申请日：2014-01-16
发明人： Kai D. Feng , Jong-ru Guo , Trushil N. Shah , Ping-Chuan Wang , Zhijian Yang
摘要： A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.
摘要翻译： 时钟相移检测器电路可以包括接收第一和第二时钟信号的相位检测器，由此相位检测器基于第一和第二时钟信号之间的相位差产生相位信号。 第一积分器耦合到相位检测器，接收相位信号，并产生积分相位信号。 第二积分器接收第一时钟信号并产生积分的第一时钟信号。 比较器耦合到第一和第二积分器，由此比较器接收积分相位信号和集成的第一时钟信号。 然后，比较器可以产生控制信号，该控制信号基于积分相位信号和集成的第一时钟信号之间的幅度比较来检测第一和第二时钟信号的相位差与优化的相位差之间的变化。
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公开(公告)号：US08638124B1
公开(公告)日：2014-01-28
申请号：US13707748
申请日：2012-12-07
发明人： Kai D. Feng , Jon-ru Guo , Trushil N. Shah , Ping-Chuan Wang , Zhijian Yang
CPC分类号： G01R25/00 , G01R31/31727 , G01R31/318552 , H03K5/13 , H03L7/081 , H03L7/085
摘要： A clock phase shift detector circuit may include a phase detector for generating a phase signal based on a phase difference between first and second clock signals. A current mirror having a first, a second, and a third integrator may be coupled to the phase detector, whereby the first integrator integrates the first clock signal and generates a first voltage, the second integrator integrates the first clock signal and generates a second voltage, and the third integrator integrates the phase signal and generates a third voltage. A first comparator receives the first and the third voltage, and generates a first control signal. A second comparator receives the second and the third voltage, and generates a second control signal. The first and second control signals may detect a change between the phase difference of the first and the second clock signal and an optimized phase difference.
摘要翻译： 时钟相移检测器电路可以包括相位检测器，用于基于第一和第二时钟信号之间的相位差产生相位信号。 具有第一，第二和第三积分器的电流镜可以耦合到相位检测器，由此第一积分器对第一时钟信号进行积分并产生第一电压，第二积分器对第一时钟信号进行积分并产生第二电压 并且第三积分器对相位信号进行积分并产生第三电压。 第一比较器接收第一和第三电压，并产生第一控制信号。 第二比较器接收第二和第三电压，并产生第二控制信号。 第一和第二控制信号可以检测第一和第二时钟信号的相位差和优化的相位差之间的变化。
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