公开(公告)号：US20240005080A1

公开(公告)日：2024-01-04

申请号：US17809600

申请日：2022-06-29

Applicant: International Business Machines Corporation

Inventor： LOUIS ZUOGUANG LIU ,  Nianzheng Cao ,  Sae Kyu Lee ,  Zhibin Ren

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2111/20

Abstract: Aspects of the invention include systems and methods configured to provide parasitic capacitance-aware dummy metal fill methodologies. A non-limiting example computer-implemented method includes selecting one or more layers in a circuit design layout for interlayer parasitic capacitance reduction. One or more dummy metal shapes in each of the one or more layers selected for interlayer parasitic capacitance reduction is adjusted (e.g., trimmed, moved, and/or reshaped). One or more adjusted dummy metal shapes are modified until the circuit design layout satisfies design rule checking (DRC) analysis and timing is closed.