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公开(公告)号：US11960422B2
公开(公告)日：2024-04-16
申请号：US17431739
申请日：2019-03-28
Applicant: Intel Corporation
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: Systems, apparatuses and methods may provide for a frontend driver that notifies a hypervisor of a map request from a guest driver of a device, wherein the device is passed through to and directly controlled by a virtual machine, and wherein the map request is associated with an attempt of the device to access a guest memory page in a virtualized execution environment. The frontend driver may also determine whether the guest memory page is pinned and send a map hypercall to the hypervisor if the guest memory page is not pinned. Additionally, the hypervisor may determine that the guest memory page is pinned, determine, based on a direct memory access (DMA) bitmap, that an unmap request from the guest driver has been issued, and unpin the guest memory page.
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公开(公告)号：US20210216365A1
公开(公告)日：2021-07-15
申请号：US17058309
申请日：2018-09-19
Applicant: Intel Corporation
Abstract: An embodiment of a semiconductor package apparatus may include technology to manage one or more virtual graphic processor units, and co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions. Other embodiments are disclosed and claimed.
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公开(公告)号：US20220129399A1
公开(公告)日：2022-04-28
申请号：US17431739
申请日：2019-03-28
Applicant: Intel Corporation
IPC: G06F13/28
Abstract: Systems, apparatuses and methods may provide for a frontend driver that notifies a hypervisor of a map request from a guest driver of a device, wherein the device is passed through to and directly controlled by a virtual machine, and wherein the map request is associated with an attempt of the device to access a guest memory page in a virtualized execution environment. The frontend driver may also determine whether the guest memory page is pinned and send a map hypercall to the hypervisor if the guest memory page is not pinned. Additionally, the hypervisor may determine that the guest memory page is pinned, determine, based on a direct memory access (DMA) bitmap, that an unmap request from the guest driver has been issued, and unpin the guest memory page.
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Patent Agency Ranking
公开(公告)号：US20240202025A1
公开(公告)日：2024-06-20
申请号：US18394232
申请日：2023-12-22
Applicant: Intel Corporation
CPC classification number: G06F9/4881 , G06F9/3004 , G06F9/30079 , G06F9/505 , G06F9/5077
Abstract: An embodiment of a semiconductor package apparatus may include technology to manage one or more virtual graphic processor units, and co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions. Other embodiments are disclosed and claimed.
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公开(公告)号：US11907377B2
公开(公告)日：2024-02-20
申请号：US17251307
申请日：2018-10-30
Applicant: Intel Corporation
CPC classification number: G06F21/577 , G06F21/84 , G06T1/20 , G06T1/60 , G06F2221/034
Abstract: Systems, apparatuses and methods may provide for technology that sets a write protection flag in a guest command buffer associated with a virtual machine and injects a semaphore command into a shadow command buffer in response to a fault. The fault is to correspond to a write of a graphics command to the guest command buffer by code executing in graphics hardware. In one example, the technology also conducts a security scan of the graphics command in response to a context switch in the graphics hardware, wherein the context switch is to be associated with the semaphore command.
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公开(公告)号：US20210256139A1
公开(公告)日：2021-08-19
申请号：US17251307
申请日：2018-10-30
Applicant: Intel Corporation
Abstract: Systems, apparatuses and methods may provide for technology that sets a write protection flag in a guest command buffer associated with a virtual machine and injects a semaphore command into a shadow command buffer in response to a fault. The fault is to correspond to a write of a graphics command to the guest command buffer by code executing in graphics hardware. In one example, the technology also conducts a security scan of the graphics command in response to a context switch in the graphics hardware, wherein the context switch is to be associated with the semaphore command.
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公开(公告)号：US12182899B2
公开(公告)日：2024-12-31
申请号：US17598267
申请日：2019-06-24
Applicant: Intel Corporation
Abstract: An apparatus and method for scheduling workloads across virtualized graphics processors. For example, one embodiment of a graphics processing apparatus comprises first graphics processing resources to process graphics commands and execute graphics data; workload scheduling circuitry to schedule workloads for execution on the first graphics processing resources; and workload queuing circuitry to implement a local queue to store local workload entries, each local workload entry associated with a locally-submitted workload and an external workload queue to store external workload entries, each external workload entry associated with an externally-submitted workload submitted for execution by an external graphics processing apparatus, in one embodiment, the workload scheduling circuitry schedules the locally-submitted workloads identified in the local queue and externally-submitted workloads identified in the external workload queue for processing by specified portions of the first graphics processing resources.
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公开(公告)号：US11900157B2
公开(公告)日：2024-02-13
申请号：US17058309
申请日：2018-09-19
Applicant: Intel Corporation
CPC classification number: G06F9/4881 , G06F9/3004 , G06F9/30079 , G06F9/505 , G06F9/5077
Abstract: An embodiment of a semiconductor package apparatus may include technology to manage one or more virtual graphic processor units, and co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions. Other embodiments are disclosed and claimed.
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