公开(公告)号：US20240347618A1

公开(公告)日：2024-10-17

申请号：US18755189

申请日：2024-06-26

Applicant: Intel Corporation

Inventor： Christine RADLINGER ,  Tongtawee WACHARASINDHU ,  Andre BARAN ,  Kiran CHIKKADI ,  Devin MERRILL ,  Nilesh DENDGE ,  David J. TOWNER ,  Christopher KENYON

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/517 ,  H01L27/0886 ,  H01L29/42364

Abstract: Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.

公开(公告)号：US20240332394A1

公开(公告)日：2024-10-03

申请号：US18129651

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： David N. GOLDSTEIN ,  David J. TOWNER ,  Dax M. CRUM ,  Omair SAADAT ,  Dan S. LAVRIC ,  Orb ACTON ,  Tongtawee WACHARASINDHU ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/4908 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having a multi-layer molybdenum metal gate stack are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A PMOS gate stack is over the first vertical arrangement of horizontal nanowires, the PMOS gate stack having a multi-layer molybdenum structure on a first gate dielectric. An NMOS gate stack is over the second vertical arrangement of horizontal nanowires, the NMOS gate stack having the multi-layer molybdenum structure or an N-type conductive layer on a second gate dielectric.