公开(公告)号：US11681529B2

公开(公告)日：2023-06-20

申请号：US17410934

申请日：2021-08-24

Applicant: Intel Corporation

Inventor： Swagath Venkataramani ,  Dipankar Das ,  Sasikanth Avancha ,  Ashish Ranjan ,  Subarno Banerjee ,  Bharat Kaul ,  Anand Raghunathan

IPC: G06F12/14 ,  G06F9/30 ,  G06N3/04 ,  G06N3/084 ,  G06N3/063 ,  G06F9/52 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/52 ,  G06N3/04 ,  G06N3/063 ,  G06N3/084

Abstract: Systems, methods, and apparatuses relating to access synchronization in a shared memory are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, and an execution unit to execute the decoded instruction to: receive a first input operand of a memory address to be tracked and a second input operand of an allowed sequence of memory accesses to the memory address, and cause a block of a memory access that violates the allowed sequence of memory accesses to the memory address. In one embodiment, a circuit separate from the execution unit compares a memory address for a memory access request to one or more memory addresses in a tracking table, and blocks a memory access for the memory access request when a type of access violates a corresponding allowed sequence of memory accesses to the memory address for the memory access request.

公开(公告)号：US11106464B2

公开(公告)日：2021-08-31

申请号：US16317501

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Swagath Venkataramani ,  Dipankar Das ,  Sasikanth Avancha ,  Ashish Ranjan ,  Subarno Banerjee ,  Bharat Kaul ,  Anand Raghunathan

IPC: G06F9/30 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  G06F9/52 ,  G06F9/38

Abstract: Systems, methods, and apparatuses relating to access synchronization in a shared memory are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, and an execution unit to execute the decoded instruction to: receive a first input operand of a memory address to be tracked and a second input operand of an allowed sequence of memory accesses to the memory address, and cause a block of a memory access that violates the allowed sequence of memory accesses to the memory address. In one embodiment, a circuit separate from the execution unit compares a memory address for a memory access request to one or more memory addresses in a tracking table, and blocks a memory access for the memory access request when a type of access violates a corresponding allowed sequence of memory accesses to the memory address for the memory access request.