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公开(公告)号:US20240305769A1
公开(公告)日:2024-09-12
申请号:US18665184
申请日:2024-05-15
Applicant: Intel Corporation
Inventor: Jason Daniel Tanner , James Holland , Stanley Jacob Baran , Satya Yedidi , Penne Yat-Pei Lee , Sumit Bhatia
IPC: H04N19/103 , H04N19/136 , H04N19/172 , H04N19/177
CPC classification number: H04N19/103 , H04N19/136 , H04N19/172 , H04N19/177
Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed of adaptive configurations of video encoder preset modes. An example apparatus comprising interface circuitry to obtain a video to be encoded, instructions, and at least one processor circuit to be programmed by the instructions to configure a video encoder to encode a first frame of the video based on a first preset mode of a plurality of preset modes associated respectively with a plurality of different relative encoder performance targets, select a second preset mode of the plurality of preset modes based on one or more characteristics associated with a second frame of the video, the second preset mode different from the first preset mode, and configure the video encoder to encode the second frame based on the second preset mode.
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公开(公告)号:US20220329835A1
公开(公告)日:2022-10-13
申请号:US17853719
申请日:2022-06-29
Applicant: Intel Corporation
Inventor: Satya Yedidi , Srivallaba Mysore , Shriram Deshpande
IPC: H04N19/423 , H04N19/105 , H04N19/88 , H04N19/176
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to implement predictor prefetching in video encoding. The example apparatus includes processor circuitry to perform operations to instantiate a predictor list generator circuitry and a predictor prefetch circuitry. The example predictor list generator circuitry to obtain predictor candidates indicating memory locations storing reference blocks from a previous block and sort the predictor candidates in a priority order. The example predictor prefetch circuitry to send cache line requests to the memory corresponding to at least some the predictor candidates that satisfy a threshold priority value. The example predictor prefetch circuitry to send the cache line requests to the memory before a reference block winner of the previous block is determined.
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公开(公告)号:US20190139184A1
公开(公告)日:2019-05-09
申请号:US16235641
申请日:2018-12-28
Applicant: Intel Corporation
Inventor: Atthar Mohammed , Hiu-Fai Chan , Hyeong-Seok Ha , Jong Dae Oh , Karthik Nagasubramanian , Ping Liu , Samuel Wong , Satya Yedidi , Sumit Mohan , Vidhya Krishnan , Pavan Kumar Saranu , Ashokanand N
IPC: G06T1/20 , H04N19/42 , H04N19/30 , G06F9/38 , H04N19/172
Abstract: Methods, apparatuses and systems may provide for technology that processes portions of video frames in different hardware pipes. More particularly, implementations relate to technology that provides splitting of a frame into columns or rows and processing each of these in different hardware pipes and managing the dependency in hardware. Such operations may achieve this support while at the same time providing enough flexibility to use these pipes independently when the higher performance is not required.
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