公开(公告)号：US20220244996A1

公开(公告)日：2022-08-04

申请号：US17717859

申请日：2022-04-11

申请人： INTEL CORPORATION

发明人： Ankush VARMA ,  Nikhil GUPTA ,  Vasudevan SRINIVASAN ,  Krishnakanth SISTLA ,  Nilanjan PALIT ,  Abhinav KARHU ,  Eugene GORBATOV ,  Eliezer WEISSMANN

IPC分类号： G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

摘要： An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

公开(公告)号：US20210303357A1

公开(公告)日：2021-09-30

申请号：US16833595

申请日：2020-03-28

申请人： Intel Corporation

发明人： Ankush VARMA ,  Nikhil GUPTA ,  Vasudevan SRINIVASAN ,  Krishnakanth SISTLA ,  Nilanjan PALIT ,  Abhinav KARHU ,  Eugene GORBATOV ,  Eliezer WEISSMANN

IPC分类号： G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

摘要： An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

公开(公告)号：US20200225724A1

公开(公告)日：2020-07-16

申请号：US16833008

申请日：2020-03-27

申请人： Intel Corporation

发明人： Chris MACNAMARA ,  John J. BROWNE ,  Tomasz KANTECKI ,  David HUNT ,  Anatoly BURAKOV ,  Srihari MAKINENI ,  Nikhil GUPTA ,  Ankush VARMA ,  Dorit SHAPIRA ,  Vasudevan SRINIVASAN ,  Bryan T. BUTTERS ,  Shrikant M. SHAH

IPC分类号： G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F1/20

摘要： Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

公开(公告)号：US20200210332A1

公开(公告)日：2020-07-02

申请号：US16816779

申请日：2020-03-12

申请人： Intel Corporation

发明人： Ian M. STEINER ,  Andrew J. HERDRICH ,  Wenhui SHU ,  Ripan DAS ,  Dianjun SUN ,  Nikhil GUPTA ,  Shruthi VENUGOPAL

IPC分类号： G06F12/06 ,  G06F11/30 ,  G06F11/34

摘要： Examples include a computing system for receiving memory class of service parameters; setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters; receiving the performance monitoring statistics from the performance monitor; and generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied by a memory bandwidth allocator to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.

公开(公告)号：US20190384348A1

公开(公告)日：2019-12-19

申请号：US16480830

申请日：2017-02-24

申请人： INTEL CORPORATION

发明人： Vasudevan SRINIVASAN ,  Krishnakanth V. SISTLA ,  Corey D. GOUGH ,  Ian M. STEINER ,  Nikhil GUPTA ,  Vivek GARG ,  Ankush VARMA ,  Sujal A. VORA ,  David P. LERNER ,  Joseph M. SULLIVAN ,  Nagasubramanian GURUMOORTHY ,  William J. BOWHILL ,  Venkatesh RAMAMURTHY ,  Chris MACNAMARA ,  John J. BROWNE ,  Ripan DAS

IPC分类号： G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455

摘要： A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.