公开(公告)号：US20240329991A1

公开(公告)日：2024-10-03

申请号：US18194327

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Martin LANGHAMMER ,  Alexander F. HEINECKE

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30025

Abstract: An apparatus of an aspect includes decoder circuitry to decode an instruction. The instruction to indicate at least one source floating-point vector, a destination storage location, and at least one value. The source floating-point vector is to have floating-point data elements. The at least one value is to indicate at least one of: (a) a number of significand bits of the floating-point data elements; (b) a number of exponent bits of the floating-point data elements; (c) exponent bias information for the floating-point data elements; or (d) any combination thereof. Execution circuitry coupled with decoder circuitry is to perform operations according to the instruction. The operations include to interpret the floating-point data elements consistent with the at least one value, perform an operation specified by the instruction on the at least one source floating-point vector to generate a result vector, and store the result vector in the destination storage location.

公开(公告)号：US20240160443A1

公开(公告)日：2024-05-16

申请号：US17985869

申请日：2022-11-13

Applicant: Intel Corporation

Inventor： Kenneth DAXER ,  Martin LANGHAMMER

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30145 ,  G06F9/3836

Abstract: A processor to perform a complex number matrix multiplication instruction indicating a first source complex number matrix having M rows by K columns of complex numbers and a second source complex number matrix having K rows by N columns of complex numbers. The processor, for each row m of the first source matrix, and for each column n of the second source matrix, to generate K complex numbers by K complex multiplications of K complex numbers of the row m of the first source matrix with K corresponding complex numbers of the column n of the second source matrix, and to combine the K generated complex numbers to generate a complex number. The generated complex number may either be stored at, or the generated complex number may be combined with a complex number at, a row m and a column n of a destination complex number matrix.

公开(公告)号：US20230367547A1

公开(公告)日：2023-11-16

申请号：US18210630

申请日：2023-06-15

Applicant: Intel Corporation

Inventor： Martin LANGHAMMER

IPC: G06F7/483 ,  G06F7/50 ,  G06F7/52

CPC classification number: G06F7/483 ,  G06F7/50 ,  G06F7/52

Abstract: A first storage location is to store a first floating-point data element. The first data element has a sign bit, an N-bit first exponent value, and M bits. A second storage location is to store a second floating-point data element that is to have a same number of bits as the first floating-point data element. The second data element has a sign bit, an N-bit first exponent value, and M bits. The N-bit first exponent value of the second data element is all zeroes and the M bits of the second data element include a significand and a second exponent value. A floating-point arithmetic unit is coupled with the first and second storage locations. The floating-point arithmetic unit is to perform either multiplication or addition on the first and second data elements to generate a result data element based at least in part on the second exponent value.

公开(公告)号：US20230333857A1

公开(公告)日：2023-10-19

申请号：US18213257

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Martin LANGHAMMER

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3888 ,  G06F9/3013

Abstract: A processor of an aspect includes an instruction unit to receive a single instruction, multiple thread (SIMT) instruction. The SIMT instruction has at least one field to provide at least one value. The at least one value is to indicate a plurality of threads that are to execute the SIMT instruction. The processor also includes a SIMT processor coupled with the instruction unit. The SIMT processor is to execute the SIMT instruction for each of the plurality of threads. Other processors, methods, systems, and machine-readable medium storing such a SIMT instructions are also disclosed.

公开(公告)号：US20190121927A1

公开(公告)日：2019-04-25

申请号：US16218179

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Martin LANGHAMMER ,  Sergey GRIBOK ,  Gregg William BAECKLER

IPC: G06F17/50 ,  H03K19/177

Abstract: A method for implementing a multiplier on a programmable logic device (PLD) is disclosed. Partial product bits of the multiplier are identified and how the partial product bits are to be summed to generate a final product from a multiplier and multiplicand are determined. Chains of PLD cells and cells in the chains of PLD cells for generating and summing the partial product bits are assigned. It is determined whether a bit in an assigned cell in an assigned chain of PLD cells is under-utilized. In response to determining that a bit is under-utilized, the assigning of the chains of PLD cells and cells for generating and summing the partial product bits are changed to improve an overall utilization of the chains of PLD cells and cells in the chains of PLD cells.

公开(公告)号：US20190042683A1

公开(公告)日：2019-02-07

申请号：US16022857

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Martin LANGHAMMER ,  Gregg William BAECKLER ,  Sergey GRIBOK

IPC: G06F17/50

Abstract: A method for designing and configuring a system on a field programmable gate array (FPGA) is disclosed. A portion of the system that is implemented greater than a predetermined number of times is identified. A structural netlist that describes how to implement the portion of the system a plurality of times on the FPGA and that leverages a repetitive nature of implementing the portion is generated. The identifying and generating is performed prior to synthesizing and placing other portions of the system that are not implemented greater than the predetermined number of time. Synthesizing, placing, and routing the other portions of the system on the FPGA is performed in accordance with the structural netlist. The FPGA is configured with a configuration file that includes a design for the system that reflects the synthesizing, placing, and routing, wherein the configuring physically transforms resources on the FPGA to implement the system.

公开(公告)号：US20240419444A1

公开(公告)日：2024-12-19

申请号：US18210635

申请日：2023-06-15

Applicant: Intel Corporation

Inventor： Martin LANGHAMMER ,  Alexander F. HEINECKE

IPC: G06F9/30

Abstract: A processor of an aspect includes decoder circuitry to decode an instruction indicating a source floating-point operand, having a floating-point data element, and indicating a destination register. The element has a sign bit, an N-bit first exponent value, and M bits. Execution circuitry of the processor is to interpret the M bits as an M-bit significand, when the N-bit first exponent value is not all zeroes or all ones, and interpret the M bits as including a second exponent value in at least one of the M bits, and a less than M-bit significand in at least one other of the M bits, when the N-bit first exponent value is either all zeroes or all ones. The execution unit is to perform an operation on the source floating-point operand to generate a result floating-point operand, and to store the result floating-point operand in the destination register.

公开(公告)号：US20190213289A1

公开(公告)日：2019-07-11

申请号：US16356713

申请日：2019-03-18

Applicant: Intel Corporation

Inventor： Gregg William BAECKLER ,  Martin LANGHAMMER ,  Sergey GRIBOK ,  Scott J. WEBER ,  Gregory STEINKE

IPC: G06F17/50 ,  G06F1/03 ,  G06F9/445

CPC classification number: G06F17/505 ,  G06F1/03 ,  G06F9/44505 ,  G06F17/5054

Abstract: A method for designing a system on a target device is disclosed. The system is synthesized from a register transfer level description. The system is placed on the target device. The system is routed on the target device. A configuration file is generated that reflects the synthesizing, placing, and routing of the system for programming the target device. A modification for the system is identified. The configuration file is modified to effectuate the modification for the system without changing the placing and routing of the system.