公开(公告)号：US12236238B2

公开(公告)日：2025-02-25

申请号：US17358867

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Li-An Tang ,  Changwon Rhee ,  Timothy R. Bauer ,  Alexander Lyashevsky ,  Jiasheng Chen

IPC: G06F9/30 ,  G06F7/44 ,  G06F7/506 ,  G06F7/57 ,  G06F9/38

Abstract: An apparatus to facilitate large integer multiplication enhancements in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a multiplication operation, wherein the multiplication operation is part of a chain of multiplication operations for a large integer multiplication; and issue a multiply and add (MAD) instruction for the multiplication operation utilizing at least one of a double precision multiplier or a 48 bit output, wherein the MAD instruction to generate an output in a single clock cycle of the processor.

公开(公告)号：US20220413848A1

公开(公告)日：2022-12-29

申请号：US17358867

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Li-An Tang ,  Changwon Rhee ,  Timothy R. Bauer ,  Alexander Lyashevsky ,  Jiasheng Chen

IPC: G06F9/30 ,  G06F7/44 ,  G06F7/506 ,  G06F7/57 ,  G06F9/38

Abstract: An apparatus to facilitate large integer multiplication enhancements in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a multiplication operation, wherein the multiplication operation is part of a chain of multiplication operations for a large integer multiplication; and issue a multiply and add (MAD) instruction for the multiplication operation utilizing at least one of a double precision multiplier or a 48 bit output, wherein the MAD instruction to generate an output in a single clock cycle of the processor.

公开(公告)号：US09952901B2

公开(公告)日：2018-04-24

申请号：US14564199

申请日：2014-12-09

Applicant: Intel Corporation

Inventor： Haihua Wu ,  Julia A. Gould ,  Li-An Tang

IPC: G06F9/46 ,  G06F9/48

CPC classification number: G06F9/4893 ,  Y02D10/24

Abstract: Described herein are technologies related to enforcing thread dependency using a hybrid scoreboard. An encoded video information that includes a plurality of threads is received, a first set and a second set of threads from the plurality of thread is determined, the first and second sets of threads are assigned to a hardware and a software, respectively, and dependency threads in the first and second sets of threads is enforced.

公开(公告)号：US09805440B2

公开(公告)日：2017-10-31

申请号：US15025901

申请日：2013-11-22

Applicant: INTEL CORPORATION ,  Weike Chen ,  Li-An Tang ,  Guei-Yuan Lueh ,  Hao Yuan ,  Samuel Hsu

Inventor： Weike Chen ,  Li-An Tang ,  Guei-Yuan Lueh ,  Hao Yuan ,  Samuel Hsu

IPC: G06T1/00 ,  G06T1/20 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/4843 ,  G06F9/5016 ,  G06T2200/28

Abstract: In an embodiment, at least one computer readable storage medium has instructions stored thereon for causing a system to send, from a processor to a task execution device, a first call to execute a first subroutine of a set of chained subroutines. The first subroutine may have a first subroutine output argument that includes a first token to indicate that first output data from execution of the first subroutine is intermediate data of the set of chained subroutines. The instructions are also for causing the system, responsive to inclusion of the first token in the first subroutine output argument, to enable the processor to execute one or more operations while the task execution device executes the first subroutine. Other embodiments are described and claimed.

公开(公告)号：US20250037347A1

公开(公告)日：2025-01-30

申请号：US18358297

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Jiasheng Chen ,  Supratim Pal ,  Kevin Hurd ,  Jorge E. Parra Osorio ,  Christopher Spencer ,  Takashi Nakagawa ,  Guei-Yuan Lueh ,  Pradeep K. Golconda ,  James Valerio ,  Mukundan Swaminathan ,  Nicholas Murphy ,  Clifford Gibson ,  Li-An Tang ,  Fangwen Fu ,  Kaiyu Chen ,  Buqi Cheng

IPC: G06T15/00 ,  G06F9/30

Abstract: Described herein is a graphics processor comprising an instruction cache and a plurality of processing elements coupled with the instruction cache. The plurality of processing elements include functional units configured to provide an integer pipeline to execute instructions to perform operations on integer data elements. The integer pipeline including a first multiplier and a second multiplier, the first multiplier and the second multiplier configured to execute operations for a single instruction.

公开(公告)号：US20160292877A1

公开(公告)日：2016-10-06

申请号：US13977509

申请日：2013-03-29

Applicant: Hao YUAN ,  Li-An TANG ,  INTEL CORPORATION

Inventor： Hao Yuan ,  Li-An Tang

IPC: G06T7/00 ,  G06T5/30 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06T5/30 ,  G06T2200/28 ,  G06T2207/10116 ,  G06T2207/20021 ,  G06T2207/20036 ,  G06T2210/44 ,  G06T2210/52

Abstract: Systems and methods may receive an input image for data processing, divide the input image into a plurality of blocks, each block including a plurality of rows, and each row including a plurality of pixels and process each pixel in the input image within a row in parallel with a user-defined template. In one example, the user-defined template is to include a structuring element and a row pixel mask.

Abstract translation: 系统和方法可以接收用于数据处理的输入图像，将输入图像划分成多个块，每个块包括多个行，并且每行包括多个像素，并且处理行中的输入图像中的每个像素 与用户定义的模板并行。 在一个示例中，用户定义的模板是包括结构元素和行像素掩码。