公开(公告)号：US20250047765A1

公开(公告)日：2025-02-06

申请号：US18923434

申请日：2024-10-22

Applicant: Intel Corporation

Inventor： Kent C. LUSTED

IPC: H04L69/24 ,  H04L49/00 ,  H04L49/351 ,  H04L69/324

Abstract: Examples described herein relate to a network interface comprising physical medium dependent (PMD) circuitry, the PMD circuitry to during link training of at least one lane consistent with IEEE 802.3, exit to TIME_OUT state during TRAIN_LOCAL state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, during link training for at least one lane consistent with IEEE 802.3, the PMD circuitry is to exit to TIME_OUT state during TRAIN_REMOTE state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, link training consistent with IEEE 802.3 comprises performance of the PMD control function in Section 162.8.11 of IEEE 802.3ck.

公开(公告)号：US20240064216A1

公开(公告)日：2024-02-22

申请号：US18374475

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kent C. LUSTED

IPC: H04L69/24 ,  H04L69/324 ,  H04L49/351 ,  H04L49/00

CPC classification number: H04L69/24 ,  H04L69/324 ,  H04L49/351 ,  H04L49/3054

Abstract: Examples described herein relate to a network interface comprising physical medium dependent (PMD) circuitry, the PMD circuitry to during link training of at least one lane consistent with IEEE 802.3, exit to TIME_OUT state during TRAIN_LOCAL state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, during link training for at least one lane consistent with IEEE 802.3, the PMD circuitry is to exit to TIME_OUT state during TRAIN_REMOTE state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, link training consistent with IEEE 802.3 comprises performance of the PMD control function in Section 162.8.11 of IEEE 802.3ck.

公开(公告)号：US20200259936A1

公开(公告)日：2020-08-13

申请号：US16859689

申请日：2020-04-27

Applicant: Intel Corporation

Inventor： Kent C. LUSTED

IPC: H04L29/06 ,  G06N20/00

Abstract: Examples described herein relate to a network interface comprising physical medium dependent (PMD) circuitry, the PMD circuitry to during link training of at least one lane consistent with IEEE 802.3, exit to TIME_OUT state during TRAIN_LOCAL state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, during link training for at least one lane consistent with IEEE 802.3, the PMD circuitry is to exit to TIME_OUT state during TRAIN_REMOTE state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, link training consistent with IEEE 802.3 comprises performance of the PMD control function in Section 162.8.11 of IEEE 802.3ck.

公开(公告)号：US20240235906A1

公开(公告)日：2024-07-11

申请号：US18143034

申请日：2023-05-03

Applicant: Intel Corporation

Inventor： Andrew K. LILLIE ,  Itamar LEVIN ,  Yaniv SABAG ,  Kent C. LUSTED

IPC: H04L25/49 ,  H04L25/03

CPC classification number: H04L25/4917 ,  H04L25/03012

Abstract: Examples described herein relate to an Ethernet physical layer transceiver (PHY) circuitry for use in frame communication with a remote link partner. In some example, the Ethernet PHY circuitry can include Physical Medium Dependent (PMD) circuitry and transmitter circuitry and receiver circuitry for use in the frame communication. In some examples, the PMD circuitry is to perform link training with a partner transmitter and selectively request the partner transmitter to apply a modulation scheme with precoding during the link training based on a magnitude of one or more equalizer coefficient values.

公开(公告)号：US20240205311A1

公开(公告)日：2024-06-20

申请号：US18287858

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Kent C. LUSTED

IPC: H04L69/24 ,  H04L1/00

CPC classification number: H04L69/24 ,  H04L1/0041

Abstract: Examples described herein relate to Ethernet physical layer transceiver (PHY) circuitry for use in frame communication with a remote link partner and that is to perform capabilities auto-negotiation with a link partner.

公开(公告)号：US20200052872A1

公开(公告)日：2020-02-13

申请号：US16655834

申请日：2019-10-17

Applicant: Intel Corporation

Inventor： Adee Ofir RAN ,  Kent C. LUSTED

IPC: H04L7/00

Abstract: Loop timing is performed in a Reconciliation Sublayer (RS) so that the transmit clock frequency can be adjusted to be equal to the receive clock frequency for the entire PHY (including the physical coding sublayer (PCS)). One of two partners is selected to be the timing Slave to the other. If only one partner is capable of loop timing, that partner becomes the Slave. If both partners are capable of loop timing, symmetry breaking can be used to determine which partner should become Slave.