公开(公告)号：US20190044627A1

公开(公告)日：2019-02-07

申请号：US15985136

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Mor COHEN ,  Amir MEZER ,  Golan PERRY ,  Adee Ofir RAN

IPC: H04B17/29 ,  H04B1/16 ,  H04L12/26

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for on-chip jitter tolerance testing. A receiver component includes a clock data recovery (CDR) logic circuit. The CDR logic circuit includes a controller to receive a phase signal and to output a DCO control signal; jitter injection (JINJ) logic to generate a first jitter signal at a first frequency and a first amplitude; and digitally controlled oscillator (DCO) to receive the first jitter signal applied to the DCO control signal and to output, based on the first jitter signal applied to the DCO control signal, a first DCO clock signal for on-chip jitter tolerance testing.

公开(公告)号：US20200374159A1

公开(公告)日：2020-11-26

申请号：US16894356

申请日：2020-06-05

Applicant: Intel Corporation

Inventor： Adee Ofir RAN

IPC: H04L25/03 ,  H04L25/49

Abstract: Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.

公开(公告)号：US20190260615A1

公开(公告)日：2019-08-22

申请号：US16399802

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Adee Ofir RAN

IPC: H04L25/03

Abstract: Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.

公开(公告)号：US20220141055A1

公开(公告)日：2022-05-05

申请号：US17573565

申请日：2022-01-11

Applicant: Intel Corporation

Inventor： Adee Ofir RAN

IPC: H04L25/03 ,  H04L25/49 ,  H04B10/25

Abstract: Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.

公开(公告)号：US20200052872A1

公开(公告)日：2020-02-13

申请号：US16655834

申请日：2019-10-17

Applicant: Intel Corporation

Inventor： Adee Ofir RAN ,  Kent C. LUSTED

IPC: H04L7/00

Abstract: Loop timing is performed in a Reconciliation Sublayer (RS) so that the transmit clock frequency can be adjusted to be equal to the receive clock frequency for the entire PHY (including the physical coding sublayer (PCS)). One of two partners is selected to be the timing Slave to the other. If only one partner is capable of loop timing, that partner becomes the Slave. If both partners are capable of loop timing, symmetry breaking can be used to determine which partner should become Slave.