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公开(公告)号：US20230088947A1
公开(公告)日：2023-03-23
申请号：US17993591
申请日：2022-11-23
申请人： Intel Corporation
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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公开(公告)号：US20210318932A1
公开(公告)日：2021-10-14
申请号：US17356157
申请日：2021-06-23
申请人： Intel Corporation
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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公开(公告)号：US09842015B2
公开(公告)日：2017-12-12
申请号：US14040092
申请日：2013-09-27
申请人： INTEL CORPORATION
发明人： Ashok Raj , Mohan J. Kumar , Jose A. Vargas , William G. Auld , Cameron B. McNairy , Theodros Yigzaw , James B. Crossland , Anthony E. Luck
CPC分类号： G06F11/0772 , G06F11/0712 , G06F11/0724 , G06F11/0784 , G06F11/0793
摘要： A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.
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公开(公告)号：US20140237299A1
公开(公告)日：2014-08-21
申请号：US13997301
申请日：2011-12-29
申请人： INTEL CORPORATION
IPC分类号： G06F11/07
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/3664 , G06F21/57
摘要： Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.
摘要翻译： 本文描述了各种实施例。 一些实施例包括操作系统和平台。 该平台包括具有错误寄存器的处理器。 操作系统只能通过平台以安全的方式（例如使用平台固件）写入错误寄存器。 描述和要求保护其他实施例。
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公开(公告)号：US20200004633A1
公开(公告)日：2020-01-02
申请号：US16292085
申请日：2019-03-04
申请人： Intel Corporation
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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6.发明申请HARDWARE PROCESSORS AND METHODS TO PERFORM SELF-MONITORING DIAGNOSTICS TO PREDICT AND DETECT FAILURE 审中-公开硬件处理器和执行自我诊断诊断和检测故障的方法公开(公告)号：US20160378628A1
公开(公告)日：2016-12-29
申请号：US14752821
申请日：2015-06-26
申请人： Intel Corporation
发明人： Hang T. Nguyen , Gordon McFadden , Travis J. White , Scott P. Bobholz , Edwin Verplanke , Steven C. Franks , Vivek Garg , Ashok Raj , Guy G. Sotomayor , Jose A. Vargas , Pradeepsunder Ganesh , Stephen T. Palermo
IPC分类号： G06F11/273 , G06F11/22
CPC分类号： G06F11/2236 , G06F11/008 , G06F11/27
摘要： Hardware processors and methods to perform self-monitoring diagnostics to predict and detect failure are described. In one embodiment, a hardware processor includes a plurality of cores, and a diagnostic hardware unit to isolate a core of the plurality of cores at run-time, perform a stress test on an isolated core, determine a stress factor from a result of the stress test, and store the stress factor in a data storage device.
摘要翻译： 描述了执行自我监视诊断以预测和检测故障的硬件处理器和方法。 在一个实施例中，硬件处理器包括多个核心，以及诊断硬件单元，用于在运行时间隔离所述多个核心的核心，在隔离的核心上执行压力测试，从所述核心的结果中确定压力因素 压力测试，并将应力因子存储在数据存储设备中。
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公开(公告)号：US20160343453A1
公开(公告)日：2016-11-24
申请号：US15226863
申请日：2016-08-02
申请人： Intel Corporation
CPC分类号： G11C29/36 , G11C29/18 , G11C29/38 , G11C29/44 , G11C29/56008
摘要： Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.
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公开(公告)号：US11048587B2
公开(公告)日：2021-06-29
申请号：US16292085
申请日：2019-03-04
申请人： Intel Corporation
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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公开(公告)号：US09798556B2
公开(公告)日：2017-10-24
申请号：US14981388
申请日：2015-12-28
申请人： INTEL CORPORATION
发明人： Mani Ayyar , Eric Richard Delano , Ioannis Y. Schoinas , Akhilesh Kumar , Doddaballapur Jayasimha , Jose A. Vargas
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.
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