公开(公告)号：US20230198550A1

公开(公告)日：2023-06-22

申请号：US17552409

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Hechen WANG ,  Andrey BELOGOLOVY ,  Richard DORRANCE ,  Deepak DASALUKUNTE

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/00 ,  G04F10/00

CPC classification number: H03M13/1177 ,  H03M13/1515 ,  H03M13/1174 ,  H03M13/6544 ,  H03M13/6597 ,  G04F10/005

Abstract: A wireless communication device, including a radiofrequency frontend, configured to wirelessly receive a radiofrequency signal; perform one or more analog baseband operations on the received radiofrequency signal, according to a radio access technology; and output an analog signal representing an output of the analog baseband operations on the received radiofrequency signal; an error corrector, configured to perform an error correction operation on the analog signal; and output an error corrected signal in analog domain; and the analog-digital converter, configured to convert the error corrected signal to digital domain.

公开(公告)号：US20240113698A1

公开(公告)日：2024-04-04

申请号：US17956844

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Richard DORRANCE ,  Peter SAGAZIO ,  Renzhi LIU ,  Hechen WANG ,  Deepak DASALUKUNTE ,  Brent R. CARLTON

IPC: H03H17/02

CPC classification number: H03H17/02 ,  H03H2218/10

Abstract: A radiofrequency frontend device includes a memory array, which includes a plurality of input lines; a plurality of output lines; and a plurality of impedance devices, each impedance device connecting an input line of the plurality of input lines to an output line of the plurality of output lines, wherein each impedance represents a filter coefficient; wherein the radiofrequency frontend device is configured to provide at each input line of the plurality of input lines a sampled voltage of an analog electric signal, each sampled voltage corresponding to a voltage of the analog electric signal during a respective time period of a plurality of time periods; and when the memory array receives the sampled voltages, the memory array is configured to modify each of the sampled voltages by a respective impedance device of the plurality of impedance devices and sum the modified sampled voltages.

公开(公告)号：US20230297149A1

公开(公告)日：2023-09-21

申请号：US17695158

申请日：2022-03-15

Applicant: Intel Corporation

Inventor： Hechen WANG

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: Embodiments herein relate to a neural network processor in a control loop, where the control loop sets an optimum supply voltage for the processor based on a measured error count or rate of the neural network. For example, if the measured error count is greater than a target level or range, the supply voltage can be increased. If the measured error count is below the target level or range, the supply voltage can be decreased. The error rate can be measured by providing an error detection circuit for one or more monitored nodes/processing units of a neural network. The error detection circuit can receive the same input data as the associated monitored processing unit, but operates on only a portion of the input data.

公开(公告)号：US20240020197A1

公开(公告)日：2024-01-18

申请号：US18372525

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Wei WU ,  Hechen WANG

IPC: G06F11/10 ,  G06F11/07 ,  G06F17/16

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F17/16

Abstract: Circuitry for a compute-in-memory (CiM) circuit or structure arranged to detect bit errors in a group of memory cells based on a summation of binary 1's included in at least one weight matrix stored to the group of memory cells, a parity value stored to another group of memory cells and a comparison of the summation or the parity value to an expected value.

公开(公告)号：US20240013850A1

公开(公告)日：2024-01-11

申请号：US18372482

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Wei WU ,  Hechen WANG

IPC: G11C29/52 ,  G11C7/18 ,  G06F7/492

CPC classification number: G11C29/52 ,  G11C7/18 ,  G06F7/4925

Abstract: A compute-in-memory (CiM) circuit or structure arranged to detect errors. Examples include detecting errors associated with weight bits stored to computational nodes included in a CiM circuit or structure based on use of complimented bit values. Examples also include detecting errors in the CiM circuit or structure based on using at least some computational nodes included in an array of computational nodes to monitor for the errors during generation of computation results by other computational nodes included in the array.