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    WIRELINE RECEIVER CIRCUITRY HAVING COLLABORATIVE TIMING RECOVERY
    4.
    发明申请
    WIRELINE RECEIVER CIRCUITRY HAVING COLLABORATIVE TIMING RECOVERY 有权
    具有协调时序恢复的线路接收器电路

    公开(公告)号：US20160182259A1

    公开(公告)日：2016-06-23

    申请号：US14573343

    申请日：2014-12-17

    Applicant: Intel Corporation

    Inventor： Tawfiq Musah ,  Gokce Keskin ,  Ganesh Balamurugan ,  James E. Jaussi ,  Bryan K. Casper

    IPC: H04L25/03 ,  H04L7/02

    CPC classification number: H04L25/03057 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/03146 ,  H04L25/14

    Abstract: Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.

    Abstract translation: 一些实施例包括具有用于接收输入信号的输入的装置和方法，用于接收具有不同相位以对输入信号进行采样的时钟信号的附加输入以及具有DFE切片的判决反馈均衡器（DFE）。 DFE片包括多个数据比较器，用于基于输入信号的采样来提供数据信息，以及多个相位误差比较器，以提供与输入信号的采样相关联的相位误差信息。 DFE切片的相位误差比较器的数量不大于DFE切片的数据比较器的数量。

    Supporting learned branch predictors
    5.
    发明授权
    Supporting learned branch predictors 有权

    公开(公告)号：US10534613B2

    公开(公告)日：2020-01-14

    申请号：US15581791

    申请日：2017-04-28

    Applicant: Intel Corporation

    Inventor： Gokce Keskin ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Tsung-Han Lin ,  Perry H. Wang ,  Hong Wang

    IPC: G06F9/38 ,  G06N3/08

    Abstract: Implementations of the disclosure provide a processing device comprising a branch predictor circuit to obtain a branch history for an application. The branch history comprising references to branching instructions associated with the application and an outcome of executing each branch. Using the branch history, a neutral network is trained to produce a weighted value for each branch of the branching instructions. Features of the branching instructions are identified based on the weighted values. Each feature identifying predictive information regarding the outcome of at least one branch of correlated branches having corresponding outcomes. A feature vector is determined based on the features. The feature vector comprises a plurality of data fields that identify an occurrence of a corresponding feature of the correlated branches with respect to the branch history. Using the feature vector, a data model is produced to determine a predicted outcome associated with the correlated branches.

    SUPPORTING LEARNED BRANCH PREDICTORS
    6.
    发明申请
    SUPPORTING LEARNED BRANCH PREDICTORS 审中-公开

    公开(公告)号：US20180314524A1

    公开(公告)日：2018-11-01

    申请号：US15581791

    申请日：2017-04-28

    Applicant: Intel Corporation

    Inventor： Gokce Keskin ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Tsung-Han Lin ,  Perry H. Wang ,  Hong Wang

    IPC: G06F9/38 ,  G06N3/08

    Abstract: Implementations of the disclosure provide a processing device comprising a branch predictor circuit to obtain a branch history for an application. The branch history comprising references to branching instructions associated with the application and an outcome of executing each branch. Using the branch history, a neutral network is trained to produce a weighted value for each branch of the branching instructions. Features of the branching instructions are identified based on the weighted values. Each feature identifying predictive information regarding the outcome of at least one branch of correlated branches having corresponding outcomes. A feature vector is determined based on the features. The feature vector comprises a plurality of data fields that identify an occurrence of a corresponding feature of the correlated branches with respect to the branch history. Using the feature vector, a data model is produced to determine a predicted outcome associated with the correlated branches.

    Instruction and logic for nearest neighbor unit
    10.
    发明授权
    Instruction and logic for nearest neighbor unit 有权

    公开(公告)号：US10387797B2

    公开(公告)日：2019-08-20

    申请号：US14865124

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Tsung-Han Lin ,  Gokce Keskin ,  Hsiang-Tsung Kung ,  She-Hwa Yen ,  Hong Wang

    IPC: G06F15/18 ,  G06N20/00 ,  G06F9/30

    Abstract: A processor includes a front end to decode an instruction, an allocator to pass the instruction to a nearest neighbor logic unit (NNLU) to execute the instruction, and a retirement unit to retire the instruction. The NNLU includes logic to determine input of the instruction for which nearest neighbors will be calculated, transform the input, retrieve candidate atoms for which the nearest neighbors will be calculated, compute distance between the candidate atoms and the input, and determine the nearest neighbors for the input based upon the computed distance.

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