公开(公告)号：US11193975B2

公开(公告)日：2021-12-07

申请号：US16024722

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Christopher J. Nelson ,  Shelby G. Rollins ,  Hiren V. Tilala ,  Matthew Hendricks ,  Sundar V. Pathy ,  Timothy J. Callahan ,  Jared Pager ,  James Neeb ,  Bradly Inman ,  Stephen Sturges

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/316 ,  G01R31/317

Abstract: Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.