知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.062 seconds)

    Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator
    1.
    发明授权
    Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator 有权

    公开(公告)号：US11907713B2

    公开(公告)日：2024-02-20

    申请号：US16729369

    申请日：2019-12-28

    Applicant: Intel Corporation

    Inventor： Kermin E. Chofleming ,  Chuanjun Zhang ,  Daniel Towner ,  Simon C. Steely, Jr. ,  Benjamin Keen

    IPC: G06F9/30 ,  G06F15/80

    CPC classification number: G06F9/3001 ,  G06F9/30181 ,  G06F15/80

    Abstract: Systems, methods, and apparatuses relating to a sign modification field for fused operations in a configurable spatial accelerator are described. In one embodiment, a hardware accelerator includes a plurality of processing elements; a network between the plurality of processing elements to transfer values between the plurality of processing elements; and a processing element of the plurality of processing elements comprising: a first plurality of input queues having a multiple bit width coupled to the network, at least one first output queue having the multiple bit width coupled to the network, operation circuitry coupled to the first plurality of input queues having the multiple bit width, a sign modification circuit coupled to the first plurality of input queues having the multiple bit width, and a configuration register within the processing element to store a configuration value comprising a sign modification field that causes the sign modification circuit to modify a sign bit of a value from the first plurality of input queues according to the sign modification field to create a sign modified value, and the configuration value causes the operation circuitry to perform a selected operation of a plurality of operations on a value from the first plurality of input queues and the sign modified value to create a resultant value, and store the resultant value in the at least one first output queue.

    LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS
    2.
    发明申请
    LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS 有权

    公开(公告)号：US20210255674A1

    公开(公告)日：2021-08-19

    申请号：US17174106

    申请日：2021-02-11

    Applicant: Intel Corporation

    Inventor： Simon C. Steely, JR. ,  Richard Dischler ,  David Bach ,  Olivier Franza ,  William J. Butera ,  Christian Karl ,  Benjamin Keen ,  Brian Leung

    IPC: G06F1/18 ,  H01L23/538 ,  G06F15/76 ,  H01L25/065 ,  G06F9/50

    Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

    LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS
    4.
    发明申请
    LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS 审中-公开

    公开(公告)号：US20190354146A1

    公开(公告)日：2019-11-21

    申请号：US16416753

    申请日：2019-05-20

    Applicant: Intel Corporation

    Inventor： Simon C. Steely, JR. ,  Richard Dischler ,  David Bach ,  Olivier Franza ,  William J. Butera ,  Christian Karl ,  Benjamin Keen ,  Brian Leung

    IPC: G06F1/18 ,  H01L23/538 ,  H01L25/065 ,  G06F9/50 ,  G06F15/76

    Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

    LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS
    5.
    发明申请
    LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS 审中-公开

    公开(公告)号：US20200371566A1

    公开(公告)日：2020-11-26

    申请号：US16862263

    申请日：2020-04-29

    Applicant: Intel Corporation

    Inventor： Simon C. Steely, JR. ,  Richard Dischler ,  David Bach ,  Olivier Franza ,  William J. Butera ,  Christian Karl ,  Benjamin Keen ,  Brian Leung

    IPC: G06F1/18 ,  H01L23/538 ,  G06F9/50 ,  H01L25/065 ,  G06F15/76

    Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

    Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator
    9.
    发明授权
    Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator 有权

    公开(公告)号：US10853073B2

    公开(公告)日：2020-12-01

    申请号：US16024849

    申请日：2018-06-30

    Applicant: Intel Corporation

    Inventor： Kermin E. Fleming, Jr. ,  Ping Zou ,  Mitchell Diamond ,  Benjamin Keen

    IPC: G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/50 ,  G06F15/82 ,  G06F9/38

    Abstract: Systems, methods, and apparatuses relating to conditional operations in a configurable spatial accelerator are described. In one embodiment, a hardware accelerator includes an output buffer of a first processing element coupled to an input buffer of a second processing element via a first data path that is to send a first dataflow token from the output buffer of the first processing element to the input buffer of the second processing element when the first dataflow token is received in the output buffer of the first processing element; an output buffer of a third processing element coupled to the input buffer of the second processing element via a second data path that is to send a second dataflow token from the output buffer of the third processing element to the input buffer of the second processing element when the second dataflow token is received in the output buffer of the third processing element; a first backpressure path from the input buffer of the second processing element to the first processing element to indicate to the first processing element when storage is not available in the input buffer of the second processing element; a second backpressure path from the input buffer of the second processing element to the third processing element to indicate to the third processing element when storage is not available in the input buffer of the second processing element; and a scheduler of the second processing element to cause storage of the first dataflow token from the first data path into the input buffer of the second processing element when both the first backpressure path indicates storage is available in the input buffer of the second processing element and a conditional token received in a conditional queue of the second processing element from another processing element is a first value.

Patent Agency Ranking