公开(公告)号：US09995785B2

公开(公告)日：2018-06-12

申请号：US15475892

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Baruch Schnarch

IPC: G11C7/00 ,  G01R31/28 ,  H01L25/065 ,  H03K19/177

CPC classification number: G01R31/2853 ,  H01L25/0657 ,  H01L2225/06544 ,  H01L2225/06555 ,  H03K19/17736 ,  H03K19/1776

Abstract: Stacked semiconductor packages and methods for performing bare die testing on a functional silicon die in a stacked semiconductor package are described. In an example, a stacked semiconductor package includes a functional silicon die, a test controller having signature accumulation logic embedded therein, and a fabric to route transactions between the test controller and any of a plurality of near memory controllers of the functional silicon die.

公开(公告)号：US10484361B2

公开(公告)日：2019-11-19

申请号：US15199356

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Timothy J. Callahan ,  Baruch Schnarch ,  Hem Doshi ,  Suketu U. Bhatt

IPC: H04L29/06 ,  G06F13/42 ,  G06F11/30 ,  G06F21/85

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; a transaction originator to originate a transactions and issue the transactions onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transactions at the serial IO interface via the device fabric and return responsive transactions to the device originator based on the transactions received; signature collection logic to collect signal information based on the transactions carried by the device fabric; and a signal accumulator to generate a test signature based on the signal information collected by the signature collection logic. Other related embodiments are disclosed.

公开(公告)号：US20180181479A1

公开(公告)日：2018-06-28

申请号：US15389471

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Hem Vasant Doshi ,  Baruch Schnarch

IPC: G06F11/36 ,  G06F21/55 ,  G06F21/44 ,  G06F11/07

CPC classification number: G06F11/3604 ,  G06F8/654 ,  G06F11/0721 ,  G06F11/079 ,  G06F11/364 ,  G06F21/44 ,  G06F21/554 ,  G06F21/565 ,  G06F21/572 ,  G06F21/575 ,  G06F21/606 ,  G06F2221/034

Abstract: In one embodiment, a request may be received to load firmware on a microcontroller of a device. A firmware transfer may be initiated to load the firmware on the microcontroller. Data traffic may be monitored at one or more locations on a communication path associated with the firmware transfer. It may be determined whether the data traffic matches a digital fingerprint associated with the firmware.

公开(公告)号：US10303237B2

公开(公告)日：2019-05-28

申请号：US15468527

申请日：2017-03-24

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Baruch Schnarch

IPC: G06F1/00 ,  G06F1/3203 ,  H03L7/099 ,  G06F13/42

Abstract: Embodiments are generally directed to phase lock loop bypass for board level testing of systems. An embodiment of system includes a power management block for the system; multiple IO (input/output) blocks; a phase lock loop (PLL) block for each of the IO blocks, each of the phase lock loop blocks being switchable between providing an output of a PLL clock signal or providing a replacement clock signal as clocking for the respective IO block; and a read only memory for storage of firmware. In some embodiments, the firmware includes elements to enable operation of the plurality of IO blocks utilizing replacement clocking.

公开(公告)号：US10430314B2

公开(公告)日：2019-10-01

申请号：US15389471

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Hem Vasant Doshi ,  Baruch Schnarch

IPC: G06F11/36 ,  G06F21/55 ,  G06F21/44 ,  G06F11/07 ,  G06F21/56 ,  G06F21/57 ,  G06F8/654 ,  G06F21/60

Abstract: In one embodiment, a request may be received to load firmware on a microcontroller of a device. A firmware transfer may be initiated to load the firmware on the microcontroller. Data traffic may be monitored at one or more locations on a communication path associated with the firmware transfer. It may be determined whether the data traffic matches a digital fingerprint associated with the firmware.

公开(公告)号：US20180181757A1

公开(公告)日：2018-06-28

申请号：US15389658

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Hem Vasant Doshi ,  Baruch Schnarch

IPC: G06F21/57 ,  G06F11/36 ,  G06F13/28 ,  G06F9/44 ,  G06F21/44 ,  G06F13/42

CPC classification number: G06F21/572 ,  G06F8/61 ,  G06F8/65 ,  G06F9/4406 ,  G06F11/3604 ,  G06F13/28 ,  G06F13/4282 ,  G06F21/44

Abstract: In one embodiment, a request may be received to load firmware from an external component to a microcontroller of a device. The external component may be authenticated, and the firmware may be loaded from the external component to the microcontroller using a firmware loading controller of the device, wherein the firmware is loaded using direct memory access without accessing system memory associated with the device.

公开(公告)号：US09972611B2

公开(公告)日：2018-05-15

申请号：US15475879

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Baruch Schnarch ,  Christopher J. Nelson ,  Danka Goldin Schwabova

IPC: H01L25/18 ,  H01L25/065 ,  H01L21/66 ,  G11C11/4093 ,  G11C11/4076 ,  G11C29/00 ,  G11C11/4096

CPC classification number: H01L25/18 ,  G11C5/025 ,  G11C11/4096 ,  G11C29/025 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/78 ,  H01L22/22 ,  H01L22/32 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06596

Abstract: A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs.