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公开(公告)号：US11546241B2
公开(公告)日：2023-01-03
申请号：US17503817
申请日：2021-10-18
申请人： Intel Corporation
IPC分类号： H04L12/26 , H04L43/106 , H04L69/22 , H04L1/00
摘要： Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.
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公开(公告)号：US20200321978A1
公开(公告)日：2020-10-08
申请号：US16905200
申请日：2020-06-18
申请人： Intel Corporation
发明人： Adee Ofir Ran , Amir Mezer , Alon Meisler , Assaf Benhamou , Itamar Levin , Yoni Landau
摘要： Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.
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公开(公告)号：US09722717B2
公开(公告)日：2017-08-01
申请号：US14574482
申请日：2014-12-18
申请人： Intel Corporation
发明人： Yoni Landau , Assaf Benhamou , Adee O. Ran
CPC分类号： H04J3/0658 , H04L7/041 , H04L12/12 , H04L2007/045 , Y02D50/40 , Y02D50/42
摘要： Technologies for robust data transmission include a network port logic having a physical coding sublayer (PCS). The PCS may transmit a series of rapid alignment markers (RAMs) to a link partner, with each RAM indicative of a counter value. The PCS transitions to a sleep state if the counter value equals two and a low power idle (LPI) command is set by an upper-layer client. The PCS transitions to an active state if the counter value equals one and the LPI command is not set. The PCS may receive a low power idle symbol (LI) from the link partner and start a guard timer in response to receipt of the LI symbol. The PCS transitions to a sleep state if the guard timer expires and transitions to the active state if data other than LI is received prior to expiration of the guard timer. Other embodiments are described and claimed.
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公开(公告)号：US20190044839A1
公开(公告)日：2019-02-07
申请号：US15941854
申请日：2018-03-30
申请人： Intel Corporation
摘要： Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.
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5.发明授权公开(公告)号：US08711018B2
公开(公告)日：2014-04-29
申请号：US13781039
申请日：2013-02-28
申请人： Intel Corporation
发明人： Ehud Shoor , Dror Lazar , Assaf Benhamou
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H04J3/0608
摘要： In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括解串器，用于以第一速率接收串行数据，并响应于从反馈回路接收到的相位控制信号，输出对应于与帧对准边界对准的串行数据的并行数据帧 耦合在解串器和耦合到解串器的输出的接收器逻辑之间。 描述和要求保护其他实施例。
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公开(公告)号：US20240020256A1
公开(公告)日：2024-01-18
申请号：US18375054
申请日：2023-09-29
申请人： Intel Corporation
发明人： Kevan A. Lillie , Shlomi Lalush , Yaakov Dalsace , Adee Ofir Ran , Assaf Benhamou , David Golodni , Itay Tamir , Amir Laufer
IPC分类号： G06F13/38 , G06F13/16 , G06F13/20 , G06F9/4401 , G06F30/18
CPC分类号： G06F13/382 , G06F13/16 , G06F13/20 , G06F9/4411 , G06F30/18 , G06F2213/0026 , G06F2213/0024
摘要： Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.
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公开(公告)号：US11153191B2
公开(公告)日：2021-10-19
申请号：US15941854
申请日：2018-03-30
申请人： Intel Corporation
摘要： Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.
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公开(公告)号：US10924132B2
公开(公告)日：2021-02-16
申请号：US16324172
申请日：2017-09-08
申请人： Intel Corporation
发明人： Adee Ofir Ran , Amir Mezer , Alon Meisler , Assaf Benhamou , Itamar Levin , Yoni Landau
摘要： Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.
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公开(公告)号：US20190215008A1
公开(公告)日：2019-07-11
申请号：US16324172
申请日：2017-09-08
申请人： Intel Corporation
发明人： Adee Ofir Ran , Amir Mezer , Alon Meisler , Assaf Benhamou , Itamar Levin , Yoni Landau
CPC分类号： H03M13/015 , H03M13/09 , H03M13/13 , H03M13/15 , H03M13/1515 , H03M13/353 , H04L1/203
摘要： Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.
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公开(公告)号：US11809353B2
公开(公告)日：2023-11-07
申请号：US15476936
申请日：2017-03-31
申请人： INTEL CORPORATION
发明人： Kevan A. Lillie , Shlomi Lalush , Yaakov Dalsace , Adee Ofir Ran , Assaf Benhamou , David Golodni , Itay Tamir , Amir Laufer
IPC分类号： G06F13/20 , G06F13/38 , G06F13/16 , G06F9/4401 , G06F30/18
CPC分类号： G06F13/382 , G06F9/4411 , G06F13/16 , G06F13/20 , G06F30/18 , G06F2213/0024 , G06F2213/0026
摘要： Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.
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