公开(公告)号：US20170286110A1

公开(公告)日：2017-10-05

申请号：US15087786

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Jason M. Agron ,  Alex Merrick ,  Vineeth Mekkat

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/3832 ,  G06F12/0875 ,  G06F2212/452

Abstract: A hardware-software co-designed processor includes a front end to decode an instruction, an execution unit to execute the instruction, an auxiliary cache to store auxiliary information for consumption during execution of the instruction, an instruction blender, and a retirement unit to retire the instruction. The auxiliary information may include long immediate values, non-working instructions for emulating an untranslated instruction stream, or execution hints, and is not decoded by the front end. The auxiliary cache includes circuitry to receive the auxiliary information from a binary translator, to store the auxiliary information in the auxiliary cache, and to provide the auxiliary information to the instruction blender prior to execution. The instruction blender includes circuitry to receive the auxiliary information, to blend the instruction with the auxiliary information, and to provide the blended instruction to the execution unit. Use of the auxiliary cache may reduce fetch and decode bandwidth requirements.