公开(公告)号：US20230097793A1

公开(公告)日：2023-03-30

申请号：US17485331

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Pei-hua Wang ,  Gregory J. George ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Chieh-Jen Ku ,  Alekhya Nimmagadda

IPC: H01L29/45 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/443 ,  H01L29/66 ,  H01L27/108

Abstract: Described herein are integrated circuit devices with lined interconnects. Interconnect liners can help maintain conductivity between semiconductor devices (e.g., transistors) and the interconnects that conduct current to and from the semiconductor devices. In some embodiments, metal interconnects are lined with a tungsten liner. Tungsten liners may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.

公开(公告)号：US20220406782A1

公开(公告)日：2022-12-22

申请号：US17351301

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Albert B. Chen ,  Wilfred Gomes ,  Fatih Hamzaoglu ,  Travis W. Lajoie ,  Van H. Le ,  Alekhya Nimmagadda ,  Miriam R. Reshotko ,  Hui Jae Yoo

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/528

Abstract: An example IC device includes a frontend layer and a backend layer with a metallization stack. The metallization stack includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.