公开(公告)号：US20220084915A1

公开(公告)日：2022-03-17

申请号：US17471249

申请日：2021-09-10

Applicant: Infineon Technologies Austria AG

Inventor： Sergey Yuferev ,  Josef Hoeglauer ,  Gerhard Noebauer ,  Hao Zhuang

IPC: H01L23/495 ,  H01L25/07 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor die having opposing first and second main surfaces, a first power electrode on the first main surface and a second power electrode on the second main surface, a first lead having an inner surface attached to the first power electrode and a distal end having a first protruding side face extending substantially perpendicularly to the first main surface of the die, a second lead having an inner surface attached to the second power electrode and a distal end having a second protruding side face extending substantially perpendicularly to the second main surface of the die, and a mold compound enclosing at least part of the die and at least part of the first and second leads. The first lead includes a recess positioned in an edge of the inner surface. The second lead includes a recess positioned in an edge of the inner surface.

公开(公告)号：US20210351168A1

公开(公告)日：2021-11-11

申请号：US17307123

申请日：2021-05-04

Applicant: Infineon Technologies Austria AG

Inventor： Gerhard Noebauer ,  Sergey Yuferev

IPC: H01L25/16 ,  H01L23/50 ,  H03K17/687

Abstract: In an embodiment, a semiconductor module includes a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a voltage input (VIN) package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further includes a first capacitor pad coupled to ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch.

公开(公告)号：US20240258213A1

公开(公告)日：2024-08-01

申请号：US18629215

申请日：2024-04-08

Applicant: Infineon Technologies Austria AG

Inventor： Sergey Yuferev ,  Josef Hoeglauer ,  Gerhard Noebauer ,  Hao Zhuang

IPC: H01L23/495 ,  H01L21/56 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/49562 ,  H01L21/561 ,  H01L21/565 ,  H01L23/49537 ,  H01L23/49575 ,  H01L25/071 ,  H01L25/072 ,  H01L25/50

Abstract: A method for manufacturing a semiconductor package includes: providing a leadframe having component positions each of which includes a die pad; providing semiconductor dies each having a first power electrode on a first main surface and a second power electrode on a second main surface; mounting a respective semiconductor die onto the die pad of a respective component position of the leadframe such that the first power electrode is attached to the die pad; mounting a clip onto the dies such that the clip is attached to a respective second power electrode; embedding at least the side faces of the dies and inner surfaces of the leadframe and clip in a mold compound to form a subassembly; and cutting through the clip and leadframe at positions between neighbouring component positions.

公开(公告)号：US20230253304A1

公开(公告)日：2023-08-10

申请号：US18135771

申请日：2023-04-18

Applicant: Infineon Technologies Austria AG

Inventor： Sergey Yuferev ,  Robert Fehler ,  Angela Kessler ,  Gerhard Noebauer ,  Petteri Palm

IPC: H01L23/498 ,  H01L25/16

CPC classification number: H01L23/49844 ,  H01L25/16

Abstract: A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area.

公开(公告)号：US10811342B2

公开(公告)日：2020-10-20

申请号：US16287318

申请日：2019-02-27

Applicant: Infineon Technologies Austria AG

Inventor： Sergey Yuferev ,  Robert Fehler ,  Petteri Palm

IPC: H01L23/52 ,  H01L23/482 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.

公开(公告)号：US20190267309A1

公开(公告)日：2019-08-29

申请号：US16287318

申请日：2019-02-27

Applicant: Infineon Technologies Austria AG

Inventor： Sergey Yuferev ,  Robert Fehler ,  Petteri Palm

IPC: H01L23/482 ,  H01L23/31

Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.

公开(公告)号：US12159829B2

公开(公告)日：2024-12-03

申请号：US17877177

申请日：2022-07-29

Applicant: Infineon Technologies Austria AG

Inventor： Sergey Yuferev ,  Robert Fehler ,  Petteri Palm

IPC: H01L23/522 ,  G06F30/394 ,  G06F30/398 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528

Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer and having a first contact pad at a first surface of the semiconductor device. An outer contact pad is positioned on a lower surface of the insulating layer. A vertical redistribution structure electrically couples the first contact pad to the outer contact pad. The first contact pad has a plurality of first via sites. A first subset of the first via sites is occupied by first vias and a second subset of the first via sites remains unoccupied and forms a first via-free zone, such that the first vias are non-uniformly distributed over the first contact pad.

公开(公告)号：US20240313105A1

公开(公告)日：2024-09-19

申请号：US18603270

申请日：2024-03-13

Applicant: Infineon Technologies Austria AG

Inventor： Gerhard Thomas Nöbauer ,  Alessandro Ferrara ,  Sergey Yuferev ,  Florian Gasser

IPC: H01L29/78 ,  H01L21/762 ,  H01L23/528 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7804 ,  H01L21/76224 ,  H01L23/528 ,  H01L29/0878 ,  H01L29/66712

Abstract: The disclosure relates to a semiconductor die with a semiconductor body. The semiconductor die includes a vertical transistor device formed in a first area of the semiconductor body. The vertical transistor device includes a source region at a first side of the semiconductor body and a drain region at a second side of the semiconductor body. The semiconductor die further includes a first electrical isolation between the first area and a second area of the semiconductor body, and a diode in the second area of the semiconductor body. A cathode contact of the diode is electrically connected to the source region of the vertical transistor device.

公开(公告)号：US11973071B2

公开(公告)日：2024-04-30

申请号：US17307123

申请日：2021-05-04

Applicant: Infineon Technologies Austria AG

Inventor： Gerhard Noebauer ,  Sergey Yuferev

IPC: H01L23/538 ,  H01L23/50 ,  H01L25/16 ,  H03K17/687

CPC classification number: H01L25/16 ,  H01L23/50 ,  H01L23/5389 ,  H03K17/6871 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: In an embodiment, a semiconductor module includes a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a voltage input (VIN) package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further includes a first capacitor pad coupled to ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch.

公开(公告)号：US20240030111A1

公开(公告)日：2024-01-25

申请号：US18351170

申请日：2023-07-12

Applicant: Infineon Technologies Austria AG

Inventor： Sergey Yuferev ,  Josef Höglauer ,  Gerhard Thomas Nöbauer ,  Hao Zhuang

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/12

CPC classification number: H01L23/49575 ,  H01L21/565 ,  H01L23/49562 ,  H01L23/12 ,  H01L23/49503 ,  H01L23/49537

Abstract: A semiconductor package includes low voltage and high voltage contact pads, an output contact pad, a half-bridge circuit, and first, second and third leads. The half bridge circuit includes first and second transistor devices coupled in series at an output node. Both transistor devices have a first major surface which extends substantially perpendicularly to the low voltage contact pad, the high voltage contact pad, and the output contact pad. Both transistor devices are arranged in a device portion of the package and are mounted on a first lead, the first lead providing the output contact pad and being arranged on a first side of the device portion. The second and third leads are arranged in a common plane on a second side of the device portion that opposes the first side. The second lead provides the low voltage pad and the third second lead provides the high voltage output pad.