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公开(公告)号：US11867762B1
公开(公告)日：2024-01-09
申请号：US18056873
申请日：2022-11-18
发明人： Marcus Nuebling , Michael Krug
IPC分类号： G01R27/08 , G01R31/327 , G01R19/175
CPC分类号： G01R31/3274 , G01R19/175
摘要： A method may comprise: controlling ON/OFF switching of a power switch via a driver circuit; receiving a first signal on a detection pin associated with the power switch, wherein the first signal corresponds to a first point in time when current is not passing through the power switch and wherein the first signal indicates a first voltage drop over one or more other circuit elements; receiving a second signal on the detection pin, wherein the second signal, wherein the second signal corresponds to a second point in time when current is passing through the power switch and wherein the second signal indicates a voltage drop over the power elements; and determining the voltage drop over the power switch based on a difference between the first signal and the second signal.
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公开(公告)号：US20230170892A1
公开(公告)日：2023-06-01
申请号：US17456857
申请日：2021-11-29
IPC分类号： H03K17/0812 , H03K17/18
CPC分类号： H03K17/08122 , H03K17/18 , H03K2217/0027
摘要： Overload detection and protection for power switch circuits. For circuits with faster switching speed, fast fault detection and response to a detected overload condition may be desirable. Detection circuitry may monitor a voltage on the control terminal of one or more power switches. Based on empirical measurements, in an overload condition of a power switch circuit, e.g., a half-bridge circuit, the voltage at the control terminal may increase, and in some examples, increase to a magnitude that is greater than a supply voltage. A comparator may detect a voltage increase that exceeds a voltage magnitude threshold, output an indication to control circuitry for the power switch circuit, and the control circuitry may take action to protect the rest of the circuitry, such as reduce voltage or shut off the power switch circuit.
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公开(公告)号：US11549998B1
公开(公告)日：2023-01-10
申请号：US17377486
申请日：2021-07-16
发明人： Carmelo Giunta , Marcus Nuebling , Steffen Thiele
IPC分类号： G01R31/52 , G01R31/26 , H03K17/687
摘要： A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.
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公开(公告)号：US11539359B2
公开(公告)日：2022-12-27
申请号：US17189607
申请日：2021-03-02
IPC分类号： H03K17/082 , H02H1/00
摘要： This disclosure is directed to circuits and techniques for protecting a power switch when the power switch is turned ON. A driver circuit may detect whether the power switch is in a desaturation mode or an overcurrent state based on a signal at a detection pin, and disable the power switch in response to detecting that the power switch is in the desaturation mode or the overcurrent state. In addition, the driver circuit may detect whether the power switch is trending towards a safe operating area (SOA) limit of the power switch based on a rate of change of the signal, and disable the power switch in response to detecting that the power switch is trending towards the SOA limit.
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公开(公告)号：US20190190513A1
公开(公告)日：2019-06-20
申请号：US15847590
申请日：2017-12-19
发明人： Marcus Nuebling , Tom Roewe
IPC分类号： H03K17/081 , H02M3/07 , H03K5/1532
CPC分类号： H03K17/08112 , H02M3/07 , H03K5/1532
摘要： A multi-sense circuit includes a transistor circuit having sense nodes and a gate node, a peak detector having inputs coupled to the sense nodes of the transistor circuit and an output, and a control circuit having a gate control node coupled to the gate node of the transistor circuit and an overcurrent protection node coupled to the output of the peak detector.
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公开(公告)号：US10126353B2
公开(公告)日：2018-11-13
申请号：US14665927
申请日：2015-03-23
IPC分类号： G01R31/3187 , G01R31/26 , G05F1/00 , H01L21/00
摘要： A gate driver is described that includes a gate signal module configured to output a gate signal of the gate driver for driving a gate terminal of a semiconductor device. The gate driver further includes a test module configured to generate a simulated failure condition at a semiconductor device during a test of a monitoring and protection feature of the gate driver. The gate drier further includes a monitor module configured to output an indication of the simulated failure condition in response to detecting the simulated failure condition at the semiconductor device.
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公开(公告)号：US12014981B2
公开(公告)日：2024-06-18
申请号：US17662790
申请日：2022-05-10
发明人： Marcus Nuebling , Mathias Racki
IPC分类号： H01L23/522 , H01L27/06 , H01L49/02
CPC分类号： H01L23/5227 , H01L23/5225 , H01L27/0629 , H01L28/10
摘要： An example circuit includes a coil structure located on at least a first layer of an integrated circuit (IC); and a circuit component comprising conduction paths. The conduction paths are located on one or more layers separate from the first layer and the first layer and the one or more layers form parallel planes. The conduction paths of the circuit component are oriented to avoid eddy currents in the conduction paths caused by an electric current through the coil structure and form a patterned shield. At least some of the conduction paths define an area, and the coil structure is located within the defined area.
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8.发明公开公开(公告)号：US20240183883A1
公开(公告)日：2024-06-06
申请号：US18061001
申请日：2022-12-02
CPC分类号： G01R15/181 , G01R27/28
摘要： Circuits, devices and systems that include a low voltage test for common mode transient immunity (CMTI). The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common mode transient rejection, the first signal path should be the same as the second signal path. Differences in the resistance, inductance, and capacitance between the two signal paths may result in common mode noise being measured as a differential signal at the output terminals. Devices according to the techniques of this disclosure are configured to enter a test mode to conduct a low voltage test that outputs a measurement of CMTI at any phase of production or field use.
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公开(公告)号：US20240128973A1
公开(公告)日：2024-04-18
申请号：US18046396
申请日：2022-10-13
IPC分类号： H03K17/687 , H02M1/08 , H02M1/38 , H02P27/08 , H03K17/689
CPC分类号： H03K17/6871 , H02M1/08 , H02M1/38 , H02P27/08 , H03K17/689
摘要： A system including circuitry to communicate data across an isolation barrier of a switch driver circuit. For switch driver circuits with galvanic isolation, the circuitry of this disclosure uses the unavoidable common mode voltages caused by the coupling capacitances of the data transfer circuit to evaluate the common mode voltage characteristics, such as the slew rate of a switching event. The switch driver circuit of this disclosure may include a common mode voltage detector to detect and measure features of the unavoidable common mode voltage during a switching event, such as voltage amplitude and slew rate. The common mode voltage detector may couple to a communication interface that provides the common mode voltage information to a controller for the switch driver circuit. In some examples, based on the received information, the controller may adjust the operation of the switching circuit.
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公开(公告)号：US20230369204A1
公开(公告)日：2023-11-16
申请号：US17662790
申请日：2022-05-10
发明人： Marcus Nuebling , Mathias Racki
IPC分类号： H01L23/522 , H01L49/02 , H01L27/06
CPC分类号： H01L23/5227 , H01L23/5225 , H01L28/10 , H01L27/0629
摘要： An example circuit includes a coil structure located on at least a first layer of an integrated circuit (IC); and a circuit component comprising conduction paths. The conduction paths are located on one or more layers separate from the first layer and the first layer and the one or more layers form parallel planes. The conduction paths of the circuit component are oriented to avoid eddy currents in the conduction paths caused by an electric current through the coil structure and form a patterned shield. At least some of the conduction paths define an area, and the coil structure is located within the defined area.
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