公开(公告)号：US11307873B2

公开(公告)日：2022-04-19

申请号：US15944546

申请日：2018-04-03

Applicant: Intel Corporation

Inventor： Pablo Halpern ,  Kermin E. Fleming ,  James Sukha

IPC: G06F9/448 ,  G06F15/82

Abstract: Systems, methods, and apparatuses relating to unstructured data flow in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a data path having a first branch and a second branch, and the data path comprises at least one processing element; a switch circuit comprising a switch control input to receive a first switch control value to couple an input of the switch circuit to the first branch and a second switch control value to couple the input of the switch circuit to the second branch; a pick circuit comprising a pick control input to receive a first pick control value to couple an output of the pick circuit to the first branch and a second pick control value to couple the output of the pick circuit to a third branch of the data path; a predicate propagation processing element to output a first edge predicate value and a second edge predicate value based on (e.g., both of) a switch control value from the switch control input of the switch circuit and a first block predicate value; and a predicate merge processing element to output a pick control value to the pick control input of the pick circuit and a second block predicate value based on both of a third edge predicate value and one of the first edge predicate value or the second edge predicate value.

公开(公告)号：US10417175B2

公开(公告)日：2019-09-17

申请号：US15859466

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Kermin E. Fleming ,  Simon C. Steely, Jr. ,  Kent D. Glossop

IPC: G06F15/16 ,  G06F15/173 ,  G06F9/54

Abstract: Methods and apparatuses relating to consistency in an accelerator are described. In one embodiment, request address file (RAF) circuits are coupled to a spatial array by a first network, a memory is coupled to the RAF circuits by a second network, a RAF circuit is to not issue, into the second network, a request to the memory marked with a program order dependency on a previous request until receiving a first token generated by completion of the previous request to the memory by another RAF circuit, and a second RAF circuit is to not issue, into the second network, a second request to the memory marked with a program order dependency on a first request until receiving a second token sent by a first RAF circuit when a predetermined time period has lapsed since the first request was issued by the first RAF circuit into the second network.

公开(公告)号：US10445098B2

公开(公告)日：2019-10-15

申请号：US15721809

申请日：2017-09-30

Applicant: INTEL CORPORATION

Inventor： Kermin E. Fleming ,  Simon C. Steely ,  Kent D. Glossop

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F9/54

Abstract: Methods and apparatuses relating to privileged configuration in spatial arrays are described. In one embodiment, a processor includes processing elements; an interconnect network between the processing elements; and a configuration controller coupled to a first subset and a second, different subset of the plurality of processing elements, the first subset having an output coupled to an input of the second, different subset, wherein the configuration controller is to configure the interconnect network between the first subset and the second, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset and the second, different subset when a privilege bit is set to a first value and to allow communication on the interconnect network between the first subset and the second, different subset of the plurality of processing elements when the privilege bit is set to a second value.

公开(公告)号：US20190205284A1

公开(公告)日：2019-07-04

申请号：US15859466

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Kermin E. Fleming ,  Simon C. Steely, Jr. ,  Kent D. Glossop

IPC: G06F15/173 ,  G06F9/54

CPC classification number: G06F15/17331 ,  G06F9/542

Abstract: Methods and apparatuses relating to consistency in an accelerator are described. In one embodiment, request address file (RAF) circuits are coupled to a spatial array by a first network, a memory is coupled to the RAF circuits by a second network, a RAF circuit is to not issue, into the second network, a request to the memory marked with a program order dependency on a previous request until receiving a first token generated by completion of the previous request to the memory by another RAF circuit, and a second RAF circuit is to not issue, into the second network, a second request to the memory marked with a program order dependency on a first request until receiving a second token sent by a first RAF circuit when a predetermined time period has lapsed since the first request was issued by the first RAF circuit into the second network.

公开(公告)号：US10515049B1

公开(公告)日：2019-12-24

申请号：US15640541

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Kermin E. Fleming ,  Simon C. Steely ,  Kent D. Glossop

IPC: G11C15/00 ,  G06F15/78 ,  G06F9/30 ,  G06F9/38

Abstract: Methods and apparatuses relating to distributed memory hazard detection and error recovery are described. In one embodiment, a memory circuit includes a memory interface circuit to service memory requests from a spatial array of processing elements for data stored in a plurality of cache banks; and a hazard detection circuit in each of the plurality of cache banks, wherein a first hazard detection circuit for a speculative memory load request from the memory interface circuit, that is marked with a potential dynamic data dependency, to an address within a first cache bank of the first hazard detection circuit, is to mark the address for tracking of other memory requests to the address, store data from the address in speculative completion storage, and send the data from the speculative completion storage to the spatial array of processing elements when a memory dependency token is received for the speculative memory load request.

公开(公告)号：US10445250B2

公开(公告)日：2019-10-15

申请号：US15859454

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Kermin E. Fleming ,  Kent D. Glossop ,  Simon C. Steely

IPC: G06F12/1045

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a second operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements.

公开(公告)号：US10380063B2

公开(公告)日：2019-08-13

申请号：US15721802

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Jinjie Tang ,  Kermin E. Fleming ,  Simon C. Steely ,  Kent D. Glossop ,  Jim Sukha

IPC: H03K19/177 ,  G06F15/78 ,  G06F9/38 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to a sequencer dataflow operator of a configurable spatial accelerator are described. In one embodiment, an interconnect network between a plurality of processing elements receives an input of a dataflow graph comprising a plurality of nodes forming a loop construct, wherein the dataflow graph is overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements and at least one dataflow operator controlled by a sequencer dataflow operator of the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements and the sequencer dataflow operator generates control signals for the at least one dataflow operator in the plurality of processing elements.

公开(公告)号：US20190205263A1

公开(公告)日：2019-07-04

申请号：US15859454

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Kermin E. Fleming ,  Kent D. Glossop ,  Simon C. Steely

IPC: G06F12/1045

CPC classification number: G06F12/1054 ,  G06F2212/608 ,  G06F2212/683

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a second operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements.