公开(公告)号：US20150287159A1

公开(公告)日：2015-10-08

申请号：US14692984

申请日：2015-04-22

Applicant: INTEL CORPORATION

Inventor： HEMA CHAND NALLURI ,  ADITYA NAVALE

IPC: G06T1/20 ,  G09G5/00 ,  G06F9/52

CPC classification number: G06T1/20 ,  G06F9/48 ,  G06F9/52 ,  G06F15/167 ,  G09G5/001

Abstract: Memory-based semaphores are described that are useful for synchronizing processes between different processing engines. In one example, operations include executing a first process at a first processing engine, the executing including updating a memory register, sending a signal from the first processing engine to a second processing engine that the memory register has been updated, the signal including a memory register address to identify the updated memory register inline data and a dataword, fetching data from the memory register by the second processing engine, comparing the fetched data to the received dataword, and conditionally executing a next command of a second process at the second processing engine based on the comparison.

Abstract translation: 描述了基于内存的信号量，其用于在不同处理引擎之间同步进程。 在一个示例中，操作包括在第一处理引擎执行第一处理，执行包括更新存储器寄存器，将信号从第一处理引擎发送到存储器寄存器已被更新的第二处理引擎，该信号包括存储器 寄存器地址以识别更新的存储器寄存器在线数据和数据字，由第二处理引擎从存储器寄存器获取数据，将获取的数据与接收到的数据字进行比较，以及有条件地执行第二处理的下一个命令 基于比较。

公开(公告)号：US20160307290A1

公开(公告)日：2016-10-20

申请号：US14686476

申请日：2015-04-14

Applicant: INTEL CORPORATION

Inventor： HEMA CHAND NALLURI ,  Balaji Vembu ,  Jeffery S. Boles

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F12/00 ,  G06F12/0811 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/455 ,  G06T1/60

Abstract: A mechanism is described for facilitating multi-level nesting of batch buffers at computing devices. A method of embodiments, as described herein, includes facilitating a hardware extension to accommodate a plurality of batch buffers to engage in a multi-level nesting, where the plurality of batch buffers are associated with a graphics processor of a computing device. The method may further include facilitating the multi-level nesting of the plurality of batch buffers, where the multi-level nesting is spread over a plurality of levels associated with the plurality of batch buffers, where the plurality of levels include more than two levels of nesting associated with more than two batch buffers of the plurality of batch buffers.

Abstract translation: 描述了一种机制，用于促进计算设备上批量缓冲区的多级嵌套。 如本文所述的实施例的方法包括促进硬件扩展以容纳多个批次缓冲器以参与多级嵌套，其中多个批处理缓冲器与计算设备的图形处理器相关联。 该方法还可以包括促进多级批量缓冲器的多级嵌套，其中多级嵌套分布在与多个批处理缓冲器相关联的多个级别上，其中多个级别包括多于两级的 与多个批次缓冲器中的两个以上批处理缓冲器相关联的嵌套。