公开(公告)号：US20170004880A1

公开(公告)日：2017-01-05

申请号：US15266367

申请日：2016-09-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiangshui Miao ,  Yi Li ,  Yaxiong Zhou ,  Ronggang Xu ,  Junfeng Zhao ,  Zhulin Wei

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463

Abstract: A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter. The logical operation array is set for performing logical operation and enable to storage output level signal in one resistive random access memory after the logical operation

Abstract translation: 电阻随机存取存储器的逻辑运算阵列包括至少一个逻辑运算单元; 每个逻辑运算单元包括多个电阻随机存取存储器，多个场效应晶体管开关和一个电压转换器。 设置逻辑运算阵列用于执行逻辑运算，并且使得能够在逻辑运算之后在一个电阻随机存取存储器中存储输出电平信号

公开(公告)号：US09767900B2

公开(公告)日：2017-09-19

申请号：US15266367

申请日：2016-09-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiangshui Miao ,  Yi Li ,  Yaxiong Zhou ,  Ronggang Xu ,  Junfeng Zhao ,  Zhulin Wei

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463

Abstract: A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter. The logical operation array is set for performing logical operation and enable to storage output level signal in one resistive random access memory after the logical operation

公开(公告)号：US20170040982A1

公开(公告)日：2017-02-09

申请号：US15331209

申请日：2016-10-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiangshui Miao ,  Yi Li ,  Yaxiong Zhou ,  Ronggang Xu ,  Junfeng Zhao ,  Shujie Zhang

IPC: H03K3/3562 ,  G11C13/00

CPC classification number: H03K3/35625 ,  G11C13/0002 ,  H03K3/0372

Abstract: A latch and a D flip-flop, where the latch includes a switch, a resistive random-access memory, a bleeder circuit, and a voltage converter. The voltage converter is configured to output an output signal of the latch according to an input signal of the latch when the switch is in an on state, where the output signal remains consistent with the input signal. When the switch changes from the on state to an off state, the resistive random-access memory is configured to work together with the bleeder circuit to enable an output signal of the latch when the switch is in the off state to remain consistent with an output signal of the latch when the switch is in the on state, thereby implementing a nonvolatile latching function. A circuit structure of the latch is simple and integrity of an existing logic circuit can be improved.

Abstract translation: 锁存器和D触发器，其中锁存器包括开关，电阻随机存取存储器，泄放电路和电压转换器。 电压转换器被配置为当开关处于导通状态时根据锁存器的输入信号输出锁存器的输出信号，其中输出信号与输入信号保持一致。 当开关从导通状态变为断开状态时，电阻随机存取存储器被配置为与泄放电路一起工作，以便当开关处于断开状态时使锁存器的输出信号保持与输出一致 当开关处于导通状态时锁存器的信号，从而实现非易失性锁存功能。 锁存器的电路结构简单，可以提高现有逻辑电路的完整性。