公开(公告)号：US10178018B2

公开(公告)日：2019-01-08

申请号：US15076250

申请日：2016-03-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuval Elad ,  Alex Tal ,  Rami Zecharia ,  Alex Umansky

IPC: H04L12/727 ,  H04L12/801 ,  H04L12/863 ,  H04L12/947 ,  H04L12/861 ,  H04L12/879

Abstract: A method and devices for reducing the delay in end-to-end delivery of network packets may be achieved by having the transmission (TX) side of the device, tag each cell with a unique packet identifier and with a byte offset parameter where the tagging allows the reception (RX) side of the destination device to perform on-the-fly assembly of cells into packets by directly placing them at corresponding host buffer, and the method may be done for multiple packets concurrently, and hence store and forward buffering is not needed in either the source or the destination devices and the lowest possible end-to-end cut-through latency is achieved.

公开(公告)号：US09281053B2

公开(公告)日：2016-03-08

申请号：US14198195

申请日：2014-03-05

Applicant: Huawei Technologies Co., Ltd.

Inventor： Rami Zecharia ,  Yaron Shachar

IPC: G11C11/00 ,  G11C11/413 ,  G06F12/02 ,  G06F13/16 ,  H04L12/933 ,  H04L12/861 ,  G06F12/06

CPC classification number: G11C11/413 ,  G06F12/023 ,  G06F12/06 ,  G06F13/1684 ,  G06F2212/2532 ,  H04L49/10 ,  H04L49/90

Abstract: A memory system (1) comprising a control logic (2) adapted to receive a number n of write requests (WRs) from input ports and to receive a read request (RR) from an output port within a clock cycle of a clock signal (CLK) applied to said memory system (1), wherein n is a natural number; and n+1 memory banks (4) of a shared memory (3) adapted to store data, wherein the control logic (2) is adapted to control a memory bank occupancy level MBOL of each memory bank (4) such that the differences between memory bank occupancy levels MBOLs of the memory banks (4) are minimized.

Abstract translation: 一种存储器系统（1），包括适于从输入端口接收数量为n个写入请求（WR）的控制逻辑（2），并且在时钟信号的时钟周期内从输出端口接收读取请求（RR） CLK）施加到所述存储器系统（1），其中n是自然数; 以及适于存储数据的共享存储器（3）的n + 1个存储体（4），其中所述控制逻辑（2）适于控制每个存储体（4）的存储体占用水平MBOL， 存储体占有率级别的存储体（4）的MBOL被最小化。

公开(公告)号：US09380007B2

公开(公告)日：2016-06-28

申请号：US14182106

申请日：2014-02-17

Applicant: Huawei Technologies Co., LTD.

Inventor： Rami Zecharia ,  Alex Umansky ,  Yan Wang

IPC: H04J3/24 ,  H04L12/861 ,  H04L12/801 ,  H04L12/18 ,  H04L12/851 ,  H04L12/863

CPC classification number: H04L49/9057 ,  H04L12/185 ,  H04L47/2408 ,  H04L47/34 ,  H04L47/624

Abstract: A method for packet reassembly and reordering, comprising: receiving a cell sent by a source port, wherein the cell carries a Source Identification (SID), a packet sequence number and a cell sequence number; preprocessing the received cell according to the SID to determine whether the cell shall be inserted into a packet reassembly database; ordering cells in the packet reassembly database according to the packet sequence number to obtain a correctly ordered packet; if the correctly ordered packet is a complete packet, ordering the cells of the correctly ordered packet according to the cell sequence number to obtain correctly ordered cells; and performing a packet reassembly for the correctly ordered cells. Correspondingly, a network device and a communication system are provided.

Abstract translation: 一种用于分组重组和重新排序的方法，包括：接收由源端口发送的小区，其中所述小区携带源标识（SID），分组序列号和小区序列号; 根据SID预处理所接收的小区，以确定该小区是否应插入分组重组数据库; 根据分组序列号对分组重组数据库中的小区排序，以获得正确排序的分组; 如果正确排序的分组是完整的分组，则根据小区序列号对正确排序的分组的小区排序，以获得正确排序的小区; 以及对正确排序的单元执行分组重组。 相应地，提供网络设备和通信系统。

公开(公告)号：US20140160935A1

公开(公告)日：2014-06-12

申请号：US14182106

申请日：2014-02-17

Applicant: Huawei Technologies Co., LTD.

Inventor： Rami Zecharia ,  Alex Umansky ,  Yan Wang

IPC: H04L12/861 ,  H04L12/863 ,  H04L12/851 ,  H04L12/18

CPC classification number: H04L49/9057 ,  H04L12/185 ,  H04L47/2408 ,  H04L47/34 ,  H04L47/624

Abstract: A method for packet reassembly and reordering, comprising: receiving a cell sent by a source port, wherein the cell carries a Source Identification (SID), a packet sequence number and a cell sequence number; preprocessing the received cell according to the SID to determine whether the cell shall be inserted into a packet reassembly database; ordering cells in the packet reassembly database according to the packet sequence number to obtain a correctly ordered packet; if the correctly ordered packet is a complete packet, ordering the cells of the correctly ordered packet according to the cell sequence number to obtain correctly ordered cells; and performing a packet reassembly for the correctly ordered cells. Correspondingly, a network device and a communication system are provided.

Abstract translation: 一种用于分组重组和重新排序的方法，包括：接收由源端口发送的小区，其中所述小区携带源标识（SID），分组序列号和小区序列号; 根据SID预处理所接收的小区，以确定该小区是否应插入分组重组数据库; 根据分组序列号对分组重组数据库中的小区排序，以获得正确排序的分组; 如果正确排序的分组是完整的分组，则根据小区序列号对正确排序的分组的小区排序，以获得正确排序的小区; 以及对正确排序的单元执行分组重组。 相应地，提供网络设备和通信系统。

公开(公告)号：US20160205013A1

公开(公告)日：2016-07-14

申请号：US15076250

申请日：2016-03-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuval Elad ,  Alex Tal ,  Rami Zecharia ,  Alex Umansky

IPC: H04L12/727 ,  H04L12/947 ,  H04L12/861 ,  H04L12/801 ,  H04L12/863

CPC classification number: H04L45/121 ,  H04L47/13 ,  H04L47/18 ,  H04L47/50 ,  H04L49/25 ,  H04L49/901 ,  H04L49/9057

Abstract: A method and devices for reducing the delay in end-to-end delivery of network packets may be achieved by having the transmission (TX) side of the device, tag each cell with a unique packet identifier and with a byte offset parameter where the tagging allows the reception (RX) side of the destination device to perform on-the-fly assembly of cells into packets by directly placing them at corresponding host buffer, and the method may be done for multiple packets concurrently, and hence store and forward buffering is not needed in either the source or the destination devices and the lowest possible end-to-end cut-through latency is achieved.

Abstract translation: 用于减少网络分组的端到端传送的延迟的方法和设备可以通过使设备的传输（TX）侧标记具有唯一分组标识符的每个小区并且具有标记的字节偏移参数来实现 允许目的地设备的接收（RX）侧通过直接将它们放置在相应的主机缓冲器上来将小区即时组装成分组，并且该方法可以同时对多个分组进行，因此存储和转发缓冲是 在源或目的设备中不需要，并且实现了尽可能低的端到端切入延迟。