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公开(公告)号：US20240048438A1
公开(公告)日：2024-02-08
申请号：US18487877
申请日：2023-10-16
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Desheng Sun , Li Ding
IPC: H04L41/0686 , H04L41/0893 , H04L41/0654
CPC classification number: H04L41/0686 , H04L41/0893 , H04L41/0654
Abstract: Method and an apparatus are provided for indicating a fault status. The method includes: a first device determines N alignment marker AM groups, where the N AM groups include first indication information, the first indication information is used to indicate a fault status of R receiving logical lanes of the first device, and each of the N AM groups includes M pieces of alignment marker group lane AMGL information; and in an ith period of N periods, the first device respectively sends M pieces of AMGL information constituting an ith AM group to a second device over M transmitting logical lanes.
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公开(公告)号：US11843504B2
公开(公告)日：2023-12-12
申请号：US17542353
申请日：2021-12-03
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Desheng Sun , Li Ding
IPC: H04L41/0654 , H04L41/0686 , H04L41/0893
CPC classification number: H04L41/0686 , H04L41/0654 , H04L41/0893
Abstract: Method and an apparatus are provided for indicating a fault status. The method includes: a first device determines N alignment marker AM groups, where the N AM groups include first indication information, the first indication information is used to indicate a fault status of R receiving logical lanes of the first device, and each of the N AM groups includes M pieces of alignment marker group lane AMGL information; and in an ith period of N periods, the first device respectively sends M pieces of AMGL information constituting an ith AM group to a second device over M transmitting logical lanes.
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公开(公告)号：US09466597B2
公开(公告)日：2016-10-11
申请号：US14457935
申请日：2014-08-12
Applicant: Huawei Technologies Co., Ltd.
Inventor： Weifeng Liu , Li Ding
CPC classification number: H01L27/0248 , H01L21/4882 , H01L23/36 , H01L23/3675 , H01L23/42 , H01L24/32 , H01L25/18 , H01L2924/16152
Abstract: Embodiments of the present invention provide a chip package structure and a chip packaging method, which is related to the field of electronic technologies, and can protect chips and effectively dissipate heat for chips. The chip package structure includes a substrate, chips, and a heat dissipating lid, where the chips include at least one master chip disposed on the substrate and at least one slave chip disposed on the substrate; the heat dissipating lid is bonded to the slave chip by using a heat conducting material, and the heat dissipating lid covers the at least one slave chip; and the heat dissipating lid includes a heat dissipating window at a position corresponding to the at least one master chip. The embodiments of the present invention are applicable to multi-chip packaging.
Abstract translation: 本发明的实施例提供了与电子技术领域相关的芯片封装结构和芯片封装方法，并且可以保护芯片并有效地散热用于芯片。 芯片封装结构包括衬底，芯片和散热盖，其中芯片包括设置在衬底上的至少一个母芯片和设置在衬底上的至少一个从芯片; 散热盖通过使用导热材料结合到副芯片，散热盖覆盖至少一个从芯片; 并且所述散热盖在与所述至少一个主芯片对应的位置处包括散热窗口。 本发明的实施例可应用于多芯片封装。
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公开(公告)号：US20130081859A1
公开(公告)日：2013-04-04
申请号：US13686057
申请日：2012-11-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： Li Ding
CPC classification number: H05K1/0298 , H05K1/0266 , H05K3/4611 , H05K3/4638 , H05K2201/09781 , H05K2201/09936 , Y10T29/49126
Abstract: A multilayer circuit board is provided, which includes multiple core boards stacked together. The core board includes an insulation layer and at least one conductor layer attached together. The conductor layer includes a circuit. The core board has at least one identification conductor disposed at an edge of at least one conductor layer. The identification conductor forms an identification pattern on a side surface of the core board along a stacking direction of the core boards. The identification patterns of the multiple core boards are different from each other on the side surface of the multilayer circuit board along the stacking direction of the core boards. A manufacturing method of the multilayer circuit board is further provided.
Abstract translation: 提供了多层电路板，其包括堆叠在一起的多个芯板。 芯板包括绝缘层和连接在一起的至少一个导体层。 导体层包括电路。 芯板具有设置在至少一个导体层的边缘处的至少一个识别导体。 识别导体沿芯板的层叠方向在芯板的侧面形成识别图案。 多个核心板的识别图案在多层电路板的侧面上沿芯板的堆叠方向彼此不同。 还提供了多层电路板的制造方法。
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公开(公告)号：US20220094463A1
公开(公告)日：2022-03-24
申请号：US17457584
申请日：2021-12-03
Applicant: Huawei Technologies, Co., Ltd.
Inventor： Desheng Sun , Yongzhi Liu , Li Ding , Zhigang Zhu
IPC: H04L1/00 , H04L69/324 , H03M13/29
Abstract: A method includes: sending, by a first device, a first bit stream to a second device, where the first bit stream is sent over N logical lanes of a physical layer of the first device; sending, by the first device, a first trigger marker group to the second device, where the first trigger marker group is used to indicate that the sending of the first bit stream ends; and sending, by the first device, a second bit stream to the second device in response to the sending of the first trigger marker group, where the second bit stream is sent over P logical lanes of the physical layer of the first device, and both N and P are positive integers.
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Patent Agency Ranking
公开(公告)号：US09018531B2
公开(公告)日：2015-04-28
申请号：US13686057
申请日：2012-11-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： Li Ding
CPC classification number: H05K1/0298 , H05K1/0266 , H05K3/4611 , H05K3/4638 , H05K2201/09781 , H05K2201/09936 , Y10T29/49126
Abstract: A multilayer circuit board is provided, which includes multiple core boards stacked together. The core board includes an insulation layer and at least one conductor layer attached together. The conductor layer includes a circuit. The core board has at least one identification conductor disposed at an edge of at least one conductor layer. The identification conductor forms an identification pattern on a side surface of the core board along a stacking direction of the core boards. The identification patterns of the multiple core boards are different from each other on the side surface of the multilayer circuit board along the stacking direction of the core boards. A manufacturing method of the multilayer circuit board is further provided.
Abstract translation: 提供了多层电路板，其包括堆叠在一起的多个芯板。 芯板包括绝缘层和连接在一起的至少一个导体层。 导体层包括电路。 芯板具有设置在至少一个导体层的边缘处的至少一个识别导体。 识别导体沿芯板的层叠方向在芯板的侧面形成识别图案。 多个核心板的识别图案在多层电路板的侧面上沿芯板的堆叠方向彼此不同。 还提供了多层电路板的制造方法。
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公开(公告)号：US11606167B2
公开(公告)日：2023-03-14
申请号：US17457584
申请日：2021-12-03
Applicant: Huawei Technologies Co., Ltd.
Inventor： Desheng Sun , Yongzhi Liu , Li Ding , Zhigang Zhu
IPC: H03M13/00 , H04L1/00 , H03M13/29 , H04L69/324
Abstract: A method includes: sending, by a first device, a first bit stream to a second device, where the first bit stream is sent over N logical lanes of a physical layer of the first device; sending, by the first device, a first trigger marker group to the second device, where the first trigger marker group is used to indicate that the sending of the first bit stream ends; and sending, by the first device, a second bit stream to the second device in response to the sending of the first trigger marker group, where the second bit stream is sent over P logical lanes of the physical layer of the first device, and both N and P are positive integers.
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公开(公告)号：US20220094591A1
公开(公告)日：2022-03-24
申请号：US17542353
申请日：2021-12-03
Applicant: HUAWEI TECHNOLOGIES CO.,LTD.
Inventor： Desheng Sun , Li Ding
IPC: H04L41/0686 , H04L41/0893 , H04L41/0654
Abstract: Method and an apparatus are provided for indicating a fault status. The method includes: a first device determines N alignment marker AM groups, where the N AM groups include first indication information, the first indication information is used to indicate a fault status of R receiving logical lanes of the first device, and each of the N AM groups includes M pieces of alignment marker group lane AMGL information; and in an ith period of N periods, the first device respectively sends M pieces of AMGL information constituting an ith AM group to a second device over M transmitting logical lanes.
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公开(公告)号：US20140346661A1
公开(公告)日：2014-11-27
申请号：US14457935
申请日：2014-08-12
Applicant: Huawei Technologies, Co., Ltd.
Inventor： Weifeng Liu , Li Ding
CPC classification number: H01L27/0248 , H01L21/4882 , H01L23/36 , H01L23/3675 , H01L23/42 , H01L24/32 , H01L25/18 , H01L2924/16152
Abstract: Embodiments of the present invention provide a chip package structure and a chip packaging method, which is related to the field of electronic technologies, and can protect chips and effectively dissipate heat for chips. The chip package structure includes a substrate, chips, and a heat dissipating lid, where the chips include at least one master chip disposed on the substrate and at least one slave chip disposed on the substrate; the heat dissipating lid is bonded to the slave chip by using a heat conducting material, and the heat dissipating lid covers the at least one slave chip; and the heat dissipating lid includes a heat dissipating window at a position corresponding to the at least one master chip. The embodiments of the present invention are applicable to multi-chip packaging.
Abstract translation: 本发明的实施例提供了与电子技术领域相关的芯片封装结构和芯片封装方法，并且可以保护芯片并有效地散热用于芯片。 芯片封装结构包括衬底，芯片和散热盖，其中芯片包括设置在衬底上的至少一个母芯片和设置在衬底上的至少一个从芯片; 散热盖通过使用导热材料结合到副芯片，散热盖覆盖至少一个从芯片; 并且所述散热盖在与所述至少一个主芯片相对应的位置处包括散热窗口。 本发明的实施例可应用于多芯片封装。
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公开(公告)号：US20250007691A1
公开(公告)日：2025-01-02
申请号：US18593259
申请日：2024-03-01
Applicant: Huawei Technologies Co., Ltd.
Inventor： Li Ding , Desheng Sun , Hongjun Bi
IPC: H04L9/06
Abstract: A first communication apparatus obtains a first ciphertext data stream, and sends the first ciphertext data stream. The first ciphertext data stream includes a first alignment marker (AM) and an encrypted first data segment. At least one of some bits in a first AM lock information field in the first AM, some bits in a first lane identification information field in the first AM, or some or all bits in a first check information field in the first AM carry encryption parameter information of the first data segment.
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