-
公开(公告)号：US09466597B2
公开(公告)日：2016-10-11
申请号：US14457935
申请日：2014-08-12
发明人： Weifeng Liu , Li Ding
CPC分类号： H01L27/0248 , H01L21/4882 , H01L23/36 , H01L23/3675 , H01L23/42 , H01L24/32 , H01L25/18 , H01L2924/16152
摘要： Embodiments of the present invention provide a chip package structure and a chip packaging method, which is related to the field of electronic technologies, and can protect chips and effectively dissipate heat for chips. The chip package structure includes a substrate, chips, and a heat dissipating lid, where the chips include at least one master chip disposed on the substrate and at least one slave chip disposed on the substrate; the heat dissipating lid is bonded to the slave chip by using a heat conducting material, and the heat dissipating lid covers the at least one slave chip; and the heat dissipating lid includes a heat dissipating window at a position corresponding to the at least one master chip. The embodiments of the present invention are applicable to multi-chip packaging.
摘要翻译： 本发明的实施例提供了与电子技术领域相关的芯片封装结构和芯片封装方法，并且可以保护芯片并有效地散热用于芯片。 芯片封装结构包括衬底，芯片和散热盖，其中芯片包括设置在衬底上的至少一个母芯片和设置在衬底上的至少一个从芯片; 散热盖通过使用导热材料结合到副芯片，散热盖覆盖至少一个从芯片; 并且所述散热盖在与所述至少一个主芯片对应的位置处包括散热窗口。 本发明的实施例可应用于多芯片封装。
-
公开(公告)号：US09318407B2
公开(公告)日：2016-04-19
申请号：US14107808
申请日：2013-12-16
发明人： Weifeng Liu , Yuming Ye , Zhao Xiang , Zhi Xu
IPC分类号： H01L23/10 , H01L23/34 , H01L23/36 , H01L23/367 , H01L25/10 , H01L25/065
CPC分类号： H01L23/34 , H01L23/36 , H01L23/3672 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/73253 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/10253 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/00
摘要： A package on package (PoP) package structure is disclosed, the structure includes at least two layers of carrier boards that are packaged and stacked in sequence, wherein chips are arranged on the bottom side of the carrier boards, a heat sink is arranged on the bottom side of a carrier board other than a layer-1 carrier board, a pad welded to a system board is arranged on the bottom side of the layer-1 carrier board, and a chip on a carrier board other than a top-layer carrier board is surface-mounted onto the heat sink adjacent to the chip. The heat sink increases the heat dissipation area of the chip, enhances the heat dissipation capabilities of the PoP stacked packages massively, breaks the bottleneck of the high-density integration and miniaturization of the PoP stacked packages, and enhances the packaging density of the PoP stacked packages.
摘要翻译： 公开了一种封装（PoP）封装结构，该结构包括依次包装和堆叠的至少两层承载板，其中芯片布置在承载板的底侧，散热器布置在 在层1载体板之外的载体板的底侧，焊接到系统板的焊盘布置在层1载体板的底侧，并且在除了顶层载体之外的载体板上的芯片 板被表面安装在与芯片相邻的散热器上。 散热片增加了芯片的散热面积，大大提高了PoP堆叠封装的散热能力，打破了PoP堆叠封装高密度集成和小型化的瓶颈，提高了PoP堆叠封装的封装密度 包装
-
公开(公告)号：US09257358B2
公开(公告)日：2016-02-09
申请号：US14552674
申请日：2014-11-25
发明人： Weifeng Liu
IPC分类号： H01L23/34 , H01L23/367 , H01L23/00 , H01L25/065 , H01L25/10 , H01L23/538 , H05K1/18 , H05K3/46 , H01L25/18 , H01L23/373
CPC分类号： H01L23/34 , H01L23/367 , H01L23/3736 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/0652 , H01L25/10 , H01L25/18 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73267 , H01L2225/1035 , H01L2924/12042 , H01L2924/15311 , H05K1/185 , H05K3/4697 , H01L2924/00
摘要： A chip stacking packaging structure is provided for achieving high-density stacking and improving a heat dissipation efficiency of the chip stacking packaging structure. The chip stacking packaging structure includes a main substrate and at least one stacking substrate in which a main chip is disposed in the main substrate, at least one stacking chip is disposed on the stacking substrate, and a side edge of the stacking substrate is disposed on the main substrate, so that the stacking chip is connected to the main chip.
摘要翻译： 提供了用于实现高密度堆叠并提高芯片堆叠包装结构的散热效率的芯片堆叠封装结构。 芯片堆叠包装结构包括主基板和至少一个堆叠基板，其中主芯片设置在主基板中，至少一个堆叠芯片设置在堆叠基板上，堆叠基板的侧边缘设置在 主芯片，使堆叠芯片连接到主芯片。
-
公开(公告)号：US20150076686A1
公开(公告)日：2015-03-19
申请号：US14552674
申请日：2014-11-25
发明人： Weifeng Liu
CPC分类号： H01L23/34 , H01L23/367 , H01L23/3736 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/0652 , H01L25/10 , H01L25/18 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73267 , H01L2225/1035 , H01L2924/12042 , H01L2924/15311 , H05K1/185 , H05K3/4697 , H01L2924/00
摘要： A chip stacking packaging structure is provided for achieving high-density stacking and improving a heat dissipation efficiency of the chip stacking packaging structure. The chip stacking packaging structure includes a main substrate and at least one stacking substrate in which a main chip is disposed in the main substrate, at least one stacking chip is disposed on the stacking substrate, and a side edge of the stacking substrate is disposed on the main substrate, so that the stacking chip is connected to the main chip.
摘要翻译： 提供了用于实现高密度堆叠并提高芯片堆叠包装结构的散热效率的芯片堆叠封装结构。 芯片堆叠包装结构包括主基板和至少一个堆叠基板，其中主芯片设置在主基板中，至少一个堆叠芯片设置在堆叠基板上，堆叠基板的侧边缘设置在 主芯片，使堆叠芯片连接到主芯片。
-
公开(公告)号：US20140346661A1
公开(公告)日：2014-11-27
申请号：US14457935
申请日：2014-08-12
发明人： Weifeng Liu , Li Ding
CPC分类号： H01L27/0248 , H01L21/4882 , H01L23/36 , H01L23/3675 , H01L23/42 , H01L24/32 , H01L25/18 , H01L2924/16152
摘要： Embodiments of the present invention provide a chip package structure and a chip packaging method, which is related to the field of electronic technologies, and can protect chips and effectively dissipate heat for chips. The chip package structure includes a substrate, chips, and a heat dissipating lid, where the chips include at least one master chip disposed on the substrate and at least one slave chip disposed on the substrate; the heat dissipating lid is bonded to the slave chip by using a heat conducting material, and the heat dissipating lid covers the at least one slave chip; and the heat dissipating lid includes a heat dissipating window at a position corresponding to the at least one master chip. The embodiments of the present invention are applicable to multi-chip packaging.
摘要翻译： 本发明的实施例提供了与电子技术领域相关的芯片封装结构和芯片封装方法，并且可以保护芯片并有效地散热用于芯片。 芯片封装结构包括衬底，芯片和散热盖，其中芯片包括设置在衬底上的至少一个母芯片和设置在衬底上的至少一个从芯片; 散热盖通过使用导热材料结合到副芯片，散热盖覆盖至少一个从芯片; 并且所述散热盖在与所述至少一个主芯片相对应的位置处包括散热窗口。 本发明的实施例可应用于多芯片封装。
-
公开(公告)号：US20140097533A1
公开(公告)日：2014-04-10
申请号：US14107808
申请日：2013-12-16
发明人： Weifeng Liu , Yuming Ye , Zhao Xiang , Zhi Xu
IPC分类号： H01L25/065 , H01L23/34
CPC分类号： H01L23/34 , H01L23/36 , H01L23/3672 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/73253 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/10253 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/00
摘要： A package on package (PoP) package structure is disclosed, the structure includes at least two layers of carrier boards that are packaged and stacked in sequence, wherein chips are arranged on the bottom side of the carrier boards, a heat sink is arranged on the bottom side of a carrier board other than a layer-1 carrier board, a pad welded to a system board is arranged on the bottom side of the layer-1 carrier board, and a chip on a carrier board other than a top-layer carrier board is surface-mounted onto the heat sink adjacent to the chip. The heat sink increases the heat dissipation area of the chip, enhances the heat dissipation capabilities of the PoP stacked packages massively, breaks the bottleneck of the high-density integration and miniaturization of the PoP stacked packages, and enhances the packaging density of the PoP stacked packages.
摘要翻译： 公开了一种封装（PoP）封装结构，该结构包括依次包装和堆叠的至少两层承载板，其中芯片布置在承载板的底侧，散热器布置在 在层1载体板之外的载体板的底侧，焊接到系统板的焊盘布置在层1载体板的底侧，并且在除了顶层载体之外的载体板上的芯片 板被表面安装在与芯片相邻的散热器上。 散热片增加了芯片的散热面积，大大提高了PoP堆叠封装的散热能力，打破了PoP堆叠封装高密度集成和小型化的瓶颈，提高了PoP堆叠封装的封装密度 包装
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.015 秒)
