公开(公告)号：US11093245B2

公开(公告)日：2021-08-17

申请号：US16439335

申请日：2019-06-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Lei Fang ,  Xi Chen ,  Weiguang Cai

IPC: G06F9/30 ,  G06F13/16 ,  G06F12/08

Abstract: A computer system and a memory access technology are provided. In the computer system, when load/store instructions having a dependency relationship is processed, dependency information between a producer load/store instruction and a consumer load/store instruction can be obtained from a processor. A consumer load/store request is sent to a memory controller in the computer system based on the obtained dependency information, so that the memory controller can terminate a dependency relationship between load/store requests in the memory controller locally based on the dependency information in the received consumer load/store request, and execute the consumer load/store request.

公开(公告)号：US10740247B2

公开(公告)日：2020-08-11

申请号：US16211225

申请日：2018-12-05

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Weiguang Cai ,  Xiongli Gu ,  Lei Fang

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/1027

Abstract: A method for accessing an entry in a translation lookaside buffer and a processing chip are provided. In the method, the entry includes at least one combination entry, and the combination entry includes a virtual huge page number, a bit vector field, and a physical huge page number. The physical huge page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages. One entry is used to represent a plurality of virtual-to-physical page mappings, so that when a page table length is fixed, a quantity of entries in the TLB can be increased exponentially, thereby increasing a TLB hit probability, and reducing TLB misses. In this way, a delay in program processing can be reduced, and processing efficiency of the processing chip can be improved.

公开(公告)号：US20190324914A1

公开(公告)日：2019-10-24

申请号：US16455466

申请日：2019-06-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Lei Fang ,  Florian Longnos

IPC: G06F12/0862 ,  G06F12/1009 ,  G06F12/0831 ,  G06F12/1045

Abstract: A method for accessing a non-volatile memory comprises that an NVM controller receive a first access request from a processor and determines whether the first access request is used to access a page table. If the first access request is used to access the page table, the NVM controller obtains an AIT entry by reading a page table entry indicated by the first address information and caches the AIT entry to an AIT cache. The NVM controller monitors access of the processor to the page table, prefetches the to-be-accessed AIT entry.

公开(公告)号：US10997078B2

公开(公告)日：2021-05-04

申请号：US16455466

申请日：2019-06-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Lei Fang ,  Florian Longnos

IPC: G06F12/0862 ,  G06F12/1009 ,  G06F12/0831 ,  G06F12/1045

Abstract: A method for accessing a non-volatile memory comprises that an NVM controller receive a first access request from a processor and determines whether the first access request is used to access a page table. If the first access request is used to access the page table, the NVM controller obtains an AIT entry by reading a page table entry indicated by the first address information and caches the AIT entry to an AIT cache. The NVM controller monitors access of the processor to the page table, prefetches the to-be-accessed AIT entry.

公开(公告)号：US10795826B2

公开(公告)日：2020-10-06

申请号：US16178676

申请日：2018-11-02

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Lei Fang ,  Weiguang Cai ,  Xiongli Gu

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/0806 ,  G06F12/128 ,  G06F12/0842 ,  G06F12/1009 ,  G06F12/0811

Abstract: A translation lookaside buffer (TLB) management method and a multi-core processor are provided. The method includes: receiving, by a first core, a first address translation request; querying a TLB of the first core based on the first address translation request; determining that a first target TLB entry corresponding to the first address translation request is missing in the TLB of the first core, obtaining the first target TLB entry; determining that entry storage in the TLB of the first core is full; determining a second core from cores in an idle state in the multi-core processor; replacing a first entry in the TLB of the first core with the first target TLB entry; storing the first entry in a TLB of the second core. Accordingly, a TLB miss rate is reduced and program execution is accelerated.

公开(公告)号：US20230262195A1

公开(公告)日：2023-08-17

申请号：US18004844

申请日：2021-07-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Lei Fang ,  Yuanying Nie ,  Xingong Zhang

IPC: H04N7/01

CPC classification number: H04N7/0122

Abstract: A photographing method and an electronic device The electronic device includes a device body and a camera connected to the device body, and the device body includes a display. The camera collects a video image, obtains a video stream with first resolution based on the video image, and further obtains a photographing stream with second resolution based on the video image. The video stream and the photographing stream are transmitted to the device body through different transmission channels.