公开(公告)号：US07408832B2

公开(公告)日：2008-08-05

申请号：US11385190

申请日：2006-03-21

Applicant: Hsiang-I Huang

Inventor： Hsiang-I Huang

IPC: G11C8/00

CPC classification number: G06F13/1615 ,  G11C8/12

Abstract: A memory control method, a memory controller, and a memory device implementing the method are provided. The memory controller controls the memory device comprising a plurality of banks, and a first row in a bank is activated for access. The memory controller receives a request for access of a second row in the bank and delivers a special command to the memory device. The memory device deactivates the first row and activates the second row upon receipt of the special command.

Abstract translation: 提供了一种存储器控制方法，存储器控制器和实现该方法的存储器件。 存储器控制器控制包括多个存储体的存储器件，并且激活用于存取的存储体中的第一行。 存储器控制器接收对存储体中的第二行的访问请求，并向存储器件传送特殊命令。 存储器件在接收到特殊命令时停用第一行并激活第二行。

公开(公告)号：US07177230B1

公开(公告)日：2007-02-13

申请号：US11211861

申请日：2005-08-25

Applicant: Hsiang-I Huang

Inventor： Hsiang-I Huang

IPC: G11C8/00

CPC classification number: G11C7/1078 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222

Abstract: A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of an internal clock and generates a third count value. A first buffer uses the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after a first predetermined period. A second buffer uses the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after the first predetermined period.

公开(公告)号：US06937247B2

公开(公告)日：2005-08-30

申请号：US10947773

申请日：2004-09-22

Applicant: Eric Yean-Liu Chang ,  Hsiang-I Huang

Inventor： Eric Yean-Liu Chang ,  Hsiang-I Huang

IPC: G11C8/12 ,  G06F12/02

CPC classification number: G11C8/12

Abstract: A memory control device and a method of controlling memory transfer. The memory control device has a command decoding device, a compare logic device, a decision device, a frame buffer decode device, a frame buffer range device and a command routing device. The frame buffer range device is used to determine if the access address pointed to a graphic memory. The command-decoding device and the compare logic device are used to determine if the access address points to a memory bank range having an error-check-correction function. The decision device is used to determine if the access address points to a memory bank range having error-check-correction function but outside the graphic memory range. If the access address points to a memory bank range having error-check-correction function but outside the graphic memory range, a memory access command with error checking and correction of data is executed.

公开(公告)号：US20050035972A1

公开(公告)日：2005-02-17

申请号：US10947773

申请日：2004-09-22

Applicant: Eric Chang ,  Hsiang-I Huang

Inventor： Eric Chang ,  Hsiang-I Huang

IPC: G11C8/12 ,  G09G5/39

CPC classification number: G11C8/12

Abstract: A memory control device and a method of controlling memory transfer. The memory control device has a command decoding device, a compare logic device, a decision device, a frame buffer decode device, a frame buffer range device and a command routing device. The frame buffer range device is used to determine if the access address pointed to a graphic memory. The command-decoding device and the compare logic device are used to determine if the access address points to a memory bank range having an error-check-correction function. The decision device is used to determine if the access address points to a memory bank range having error-check-correction function but outside the graphic memory range. If the access address points to a memory bank range having error-check-correction function but outside the graphic memory range, a memory access command with error checking and correction of data is executed.

公开(公告)号：US08665665B2

公开(公告)日：2014-03-04

申请号：US13076023

申请日：2011-03-30

Applicant: Hsiang-I Huang

Inventor： Hsiang-I Huang

IPC: G11C8/18

CPC classification number: G11C11/409 ,  G11C7/1066 ,  G11C29/028 ,  G11C29/50012

Abstract: An embodiment of the invention provides a memory controller for controlling a memory. The memory controller comprises a pulse width modulation module, a voltage comparator and a duty cycle calibration device. The pulse width modulation module is suitable for receiving a clock signal to generate a first voltage. The voltage comparator is suitable for receiving and comparing a reference voltage with the first voltage to output a comparison signal. The duty cycle calibration device is suitable for adjusting a duty cycle of the clock signal according to the comparison signal.

Abstract translation: 本发明的实施例提供了一种用于控制存储器的存储器控​​制器。 存储器控制器包括脉宽调制模块，电压比较器和占空比校准装置。 脉冲宽度调制模块适于接收时钟信号以产生第一电压。 电压比较器适于接收和比较参考电压与第一电压以输出比较信号。 占空比校准装置适用于根据比较信号调整时钟信号的占空比。

公开(公告)号：US07542371B2

公开(公告)日：2009-06-02

申请号：US11644222

申请日：2006-12-21

Applicant: Hsiang-I Huang

Inventor： Hsiang-I Huang

IPC: G11C8/00

CPC classification number: G11C7/1078 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222

Abstract: A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of an internal clock and generates a third count value. A first buffer uses the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after a first predetermined period. A second buffer uses the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after the first predetermined period.

Abstract translation: 内存控制器 第一计数器由数据选通信号的上升沿触发并产生第一计数值。 第二计数器由数据选通信号的下降沿触发并产生第二计数值。 第三个计数器由内部时钟的上升沿触发，并产生第三个计数值。 第一缓冲器使用第一计数值作为用于顺序存储对应于数据选通信号的上升沿的数据的写入地址，并且在第一预定周期之后顺序地输出与第三计数值相对应的数据。 第二缓冲器使用第二计数值作为对应于数据选通信号的下降沿的数据的顺序存储的写入地址，并且在第一预定周期之后顺序输出与第三计数值相对应的数据。

公开(公告)号：US06874117B2

公开(公告)日：2005-03-29

申请号：US10068251

申请日：2002-02-06

Applicant: Eric Yean-Liu Chang ,  Hsiang-I Huang

Inventor： Eric Yean-Liu Chang ,  Hsiang-I Huang

IPC: G11C8/12 ,  H03M13/00 ,  G11C29/00

CPC classification number: G11C8/12

Abstract: A memory control device and a method of controlling memory transfer. The memory control device has a command decoding device, a compare logic device, a decision device, a frame buffer decode device, a frame buffer range device and a command routing device. The frame buffer range device is used to determine if the access address pointed to a graphic memory. The command-decoding device and the compare logic device are used to determine if the access address points to a memory bank range having an error-check-correction function. The decision device is used to determine if the access address points to a memory bank range having error-check-correction function but outside the graphic memory range. If the access address points to a memory bank range having error-check-correction function but outside the graphic memory range, a memory access command with error checking and correction of data is executed.

Abstract translation: 一种存储器控制装置和一种控制存储器传送的方法。 存储器控制装置具有命令解码装置，比较逻辑装置，判定装置，帧缓冲器解码装置，帧缓冲器范围装置和命令路由装置。 帧缓冲区范围设备用于确定访问地址是否指向图形存储器。 命令解码装置和比较逻辑装置用于确定访问地址是否指向具有错误检查校正功能的存储体范围。 判定装置用于确定访问地址是否指向具有错误检查校正功能但在图形存储器范围之外的存储体范围。 如果访问地址指向具有错误检查校正功能但在图形存储器范围之外的存储体范围，则执行具有错误检查和数据校正的存储器访问命令。

公开(公告)号：US06731565B2

公开(公告)日：2004-05-04

申请号：US10064395

申请日：2002-07-10

Applicant: Hsiang-I Huang

Inventor： Hsiang-I Huang

IPC: G11C722

CPC classification number: G06F13/1689

Abstract: A programmable memory controller has a main memory device, a command decoder, a period setting device, a command-sequencing device and a command signal output device. When the programmable memory controller needs to access data inside a memory unit, the memory controller sends out a request signal. The command decoder receives the request signal and decodes the request signal to produce command signals. The period setting device receives a control signal and decodes the control signal to produce a period setting signal. The control signal controls the maintenance period of the command signals. The command-sequencing device receives the command signals and the period setting signals to sequence the command signals. The command signal output device receives the sequenced command signals and the period setting signal so that the sequenced command signal is sent to the memory unit during the maintenance period according to indications provided by the period setting signals.

Abstract translation: 可编程存储器控制器具有主存储器件，命令解码器，周期设置器件，命令排序器件和命令信号输出器件。 当可编程存储器控制器需要访问存储器单元内的数据时，存储器控制器发出请求信号。 命令解码器接收请求信号并解码请求信号以产生命令信号。 周期设定装置接收控制信号并解码该控制信号以产生周期设定信号。 控制信号控制命令信号的维护周期。 命令排序装置接收命令信号和周期设置信号以对命令信号进行排序。 命令信号输出装置接收顺序命令信号和周期设定信号，使得根据周期设定信号提供的指示，在维护期间将排序的命令信号发送到存储器单元。

公开(公告)号：US20090319744A1

公开(公告)日：2009-12-24

申请号：US12142882

申请日：2008-06-20

Applicant: Hsiang-I Huang

Inventor： Hsiang-I Huang

IPC: G06F12/00

CPC classification number: H04N7/0132 ,  H04N5/05 ,  H04N7/0105

Abstract: A digital television, a memory controller and a method for controlling access of a memory device are provided. The digital television comprises the memory device and the memory controller. The memory controller comprises a storage buffer and a clock adjustment device. The storage buffer buffers a data read from the memory device according to a reference clock source. The clock adjustment device provides the reference clock source and determines whether to adjust the reference clock source in response to the data. The method comprises steps of: providing a reference clock source; buffering a data read from the memory device according to the reference clock source; and determining whether to adjust the reference clock source in response to the data.

Abstract translation: 提供数字电视，存储器控制器和用于控制存储器件存取的方法。 数字电视包括存储器件和存储器控制器。 存储器控制器包括存储缓冲器和时钟调整装置。 存储缓冲器根据参考时钟源缓冲从存储器件读取的数据。 时钟调整装置提供参考时钟源，并根据数据确定是否调整参考时钟源。 该方法包括以下步骤：提供参考时钟源; 根据参考时钟源缓冲从存储器件读取的数据; 以及响应于所述数据确定是否调整所述参考时钟源。

公开(公告)号：US20070242530A1

公开(公告)日：2007-10-18

申请号：US11279750

申请日：2006-04-13

Applicant: Hsiang-I Huang ,  Ta-Lun Huang

Inventor： Hsiang-I Huang ,  Ta-Lun Huang

IPC: G11C7/10

CPC classification number: G06F13/1694 ,  G06F13/1678 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1066

Abstract: A memory controller includes a first data converter for converting incoming data into a first data in which a bit width of the incoming data and a bit width of the first data corresponds to a first ratio; a second data converter for converting the incoming data into a second data where the bit width of the incoming data and a bit width of the second data corresponds to a second ratio; and a first selector, coupled to the first and second data converters, for outputting either the first data or the second data to a memory device according to a memory mode setting.

Abstract translation: 存储器控制器包括：第一数据转换器，用于将输入数据转换成其中输入数据的位宽度和第一数据的位宽度对应于第一比率的第一数据; 第二数据转换器，用于将输入数据转换成第二数据，其中输入数据的位宽和第二数据的位宽对应于第二比率; 以及耦合到第一和第二数据转换器的第一选择器，用于根据存储器模式设置将第一数据或第二数据输出到存储器件。