公开(公告)号：US10886101B2

公开(公告)日：2021-01-05

申请号：US16494595

申请日：2017-03-29

Applicant: Hitachi High-Tech Corporation

Inventor： Ryo Hirano ,  Hideo Morishita ,  Toshihide Agemura ,  Junichi Katane ,  Tsunenori Nomaguchi

IPC: H01J37/28 ,  H01J37/12 ,  H01J37/145 ,  H01J37/153

Abstract: A charged particle beam device includes: a charged particle source that emits a charged particle beam; a boosting electrode disposed between the charged particle source and a sample to form a path of the charged particle beam and to accelerate and decelerate the charged particle beam; a first pole piece that covers the boosting electrode; a second pole piece that covers the first pole piece; a first lens coil disposed outside the first pole piece and inside the second pole piece to form a first lens; a second lens coil disposed outside the second pole piece to form a second lens; and a control electrode formed between a distal end portion of the first pole piece and a distal end portion of the second pole piece to control an electric field formed between the sample and the distal end portion of the second pole piece.

公开(公告)号：US11709199B2

公开(公告)日：2023-07-25

申请号：US16967280

申请日：2018-02-06

Applicant: Hitachi High-Tech Corporation

Inventor： Tomohisa Ohtaki ,  Takayuki Mizuno ,  Ryo Hirano ,  Toru Fujimura ,  Shigehiko Kato ,  Yasuhiko Nara ,  Katsuo Ohki ,  Akira Kageyama ,  Masaaki Komori

IPC: G01R1/04 ,  G01R1/073 ,  G01R1/067 ,  G01R31/28 ,  H01L21/66

CPC classification number: G01R31/2831 ,  G01R1/0491 ,  G01R1/06755 ,  G01R1/07342 ,  H01L22/20

Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to an evaluation apparatus for a semiconductor device of the present invention, the above described problems can be solved by providing a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.

公开(公告)号：US11977099B2

公开(公告)日：2024-05-07

申请号：US16967246

申请日：2018-02-06

Applicant: Hitachi High-Tech Corporation

Inventor： Tomohisa Ohtaki ,  Takayuki Mizuno ,  Ryo Hirano ,  Toru Fujimura ,  Shigehiko Kato ,  Yasuhiko Nara ,  Katsuo Ohki ,  Akira Kageyama ,  Masaaki Komori

IPC: G01R1/04 ,  G01R31/28 ,  H01L21/66

CPC classification number: G01R1/0491 ,  G01R31/2886 ,  H01L22/34

Abstract: A method for manufacturing a semiconductor device in which probes and the layout of the electrode pads of a test element group (TEG) are associated is provided. As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Thus, it is necessary to associate the probes and the layout of the electrode pad. According to the method, a layout of a TEG electrode pad corresponding to a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology is provided.