Invention Grant
- Patent Title: Evaluation apparatus for semiconductor device
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Application No.: US16967280Application Date: 2018-02-06
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Publication No.: US11709199B2Publication Date: 2023-07-25
- Inventor: Tomohisa Ohtaki , Takayuki Mizuno , Ryo Hirano , Toru Fujimura , Shigehiko Kato , Yasuhiko Nara , Katsuo Ohki , Akira Kageyama , Masaaki Komori
- Applicant: Hitachi High-Tech Corporation
- Applicant Address: JP Tokyo
- Assignee: Hitachi High-Tech Corporation
- Current Assignee: Hitachi High-Tech Corporation
- Current Assignee Address: JP Tokyo
- Agency: Crowell & Moring LLP
- International Application: PCT/JP2018/003986 2018.02.06
- International Announcement: WO2019/155518A 2019.08.15
- Date entered country: 2020-08-04
- Main IPC: G01R1/04
- IPC: G01R1/04 ; G01R1/073 ; G01R1/067 ; G01R31/28 ; H01L21/66

Abstract:
As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to an evaluation apparatus for a semiconductor device of the present invention, the above described problems can be solved by providing a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.
Public/Granted literature
- US20210025936A1 Evaluation Apparatus for Semiconductor Device Public/Granted day:2021-01-28
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