公开(公告)号：US20020024061A1

公开(公告)日：2002-02-28

申请号：US09983143

申请日：2001-10-23

Applicant: Hitachi, Ltd.

Inventor： Masao Kondo ,  Katsuya Oda ,  Katsuyoshi Washio

IPC: H01L031/0328

CPC classification number: H01L31/1105

Abstract: A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.

Abstract translation: 使用B掺杂Si和Ge合金作为基极的双极晶体管，其中发射极 - 基极耗尽区和基极 - 集电极耗尽区中的Ge含量大于基底层中的Ge含量。 通过使基底层两侧的发射极 - 基极耗尽区域和基极 - 集电极耗尽区中的Ge含量大于基底层中的Ge含量，可以抑制B从基极层的扩散，因为扩散系数 在Ge含量增加时，SiGe层中的B降低。

公开(公告)号：US20030006485A1

公开(公告)日：2003-01-09

申请号：US10237674

申请日：2002-09-10

Applicant: Hitachi, Ltd.

Inventor： Masao Kondo ,  Katsuya Oda ,  Katsuyoshi Washio

IPC: H01L027/082

CPC classification number: H01L31/1105

Abstract: A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.

公开(公告)号：US20010045604A1

公开(公告)日：2001-11-29

申请号：US09824225

申请日：2001-04-03

Applicant: Hitachi, Ltd.

Inventor： Katsuya Oda ,  Katsuyoshi Washio

IPC: H01L029/76 ,  H01L027/12

CPC classification number: B82Y10/00 ,  H01L21/823807 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/66439 ,  H01L29/7378 ,  H01L29/7782

Abstract: A semiconductor device having an MODFET and at least one other device formed on one identical semiconductor substrate, in which an intrinsic region for the MODFET is formed by selective growth in a groove formed on a semiconductor substrate having an insulation film on the side wall of the groove, and single-crystal silicon at the bottom of the groove, is disclosed. The step between the MODFET and the at least one other device mounted together on one identical substrate can be thereby decreased, and each of the devices can be reduced in the size and integrated to a high degree, and the interconnection length can be shortened to reduce power consumption.

Abstract translation: 一种具有MODFET和至少一个其它器件的半导体器件，其形成在一个相同的半导体衬底上，其中用于MODFET的本征区域通过在形成于半导体衬底上的沟槽中的选择性生长形成，该半导体衬底上具有绝缘膜 凹槽和沟槽底部的单晶硅。 因此，可以减少在一个相同的基板上安装在一起的MODFET与至少一个其他装置之间的台阶，并且可以将各个装置的尺寸减小到高度集成，并且可以缩短互连长度以减少 能量消耗。

公开(公告)号：US20030098465A1

公开(公告)日：2003-05-29

申请号：US10299837

申请日：2002-11-20

Applicant: Hitachi, Ltd.

Inventor： Isao Suzumura ,  Katsuya Oda ,  Katsuyoshi Washio

IPC: H01L031/0328

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: A high-speed heterojunction bipolar transistor in a large injection of electrons from the emitter and a method for production thereof. In a typical example of the SiGeC heterojunction bipolar transistor, the collector has a layer of n-type single-crystal Si and a layer of n-type single-crystal SiGe, the base is a layer of heavily doped p-type single crystal SiGeC, and the emitter is a layer of n-type single-crystal Si. At the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC, the bandgap of the p-type single-crystal SiGeC is larger than that of the layer of n-type single crystal SiGe. Even though the effective neutral base expands due to an increase in electrons injected from the emitter, no energy barrier occurs in the conduction band at the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC. Thus, the diffusion of electrons is not inhibited and it is possible to realize high-speed heterojunction bipolar transistors even in the high injection state.

Abstract translation: 从发射极大量注入电子的高速异质结双极晶体管及其制造方法。 在SiGeC异质结双极晶体管的典型实例中，集电体具有n型单晶Si层和n型单晶SiGe层，其基极是重掺杂p型单晶SiGeC层 ，发射极是n型单晶Si层。 在n型单晶SiGe层和p型单晶SiGeC层之间的异质界面处，p型单晶SiGeC的带隙大于n型单晶SiGeC层的带隙 SiGe。 即使有效的中性碱基由于从发射体注入的电子的增加而扩大，在n型单晶SiGe层与p型单晶层之间的异质界面的导带中也不发生能量势垒 SiGeC。 因此，电子的扩散不被抑制，即使在高注入状态下也可以实现高速异质结双极晶体管。

公开(公告)号：US20030045063A1

公开(公告)日：2003-03-06

申请号：US10150943

申请日：2002-05-21

Applicant: Hitachi, Ltd.

Inventor： Katsuya Oda

IPC: H01L021/331 ,  H01L021/8222 ,  H01L021/44

CPC classification number: H01L29/66431 ,  C23C16/22 ,  C23C16/54 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661 ,  H01L29/66242

Abstract: A method of manufacturing a semiconductor device comprising a plurality of single-crystal semiconductor layers formed, for example, in an opening of an insulating film, said semiconductor layers having no or very few crystal defects. The method comprises forming in a first growth chamber a first semiconductor layer of a first conductivity type in an opening of an insulating film and subsequently forming in a second growth chamber a second semiconductor layer of a second conductivity type in an opening of an insulating film, while supplying hydrogen to the surface of the substrate when the substrate is transferred from said first growth chamber to said second growth chamber.

Abstract translation: 一种制造半导体器件的方法，包括例如在绝缘膜的开口中形成的多个单晶半导体层，所述半导体层没有或很少的晶体缺陷。 该方法包括在第一生长室中在绝缘膜的开口中形成第一导电类型的第一半导体层，随后在第二生长室中在绝缘膜的开口中形成第二导电类型的第二半导体层， 同时当衬底从所述第一生长室转移到所述第二生长室时，向衬底的表面供应氢。