公开(公告)号：US06246624B1

公开(公告)日：2001-06-12

申请号：US09198726

申请日：1998-11-24

Applicant: Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

Inventor： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC: G11C700

CPC classification number: H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract translation: 本发明包括栅极和漏极与第一节点连接的第一MOS晶体管，栅极和漏极分别与第一节点和第三节点连接的第二MOS晶体管，第一电阻元件连接在第一节点之间 节点和第二节点，连接在第二节点和地电压端子之间的第二电阻元件，其输入端与第二节点连接的第一NOT电路，其输出端子是第四节点，并且连接在 第三节点和地电压端子，以及第二NOT电路，其输入端与第四节点连接，其输出端为第五节点。 因此，本发明能够以低功耗检测稳定状态的电压。

公开(公告)号：US06822493B2

公开(公告)日：2004-11-23

申请号：US10370395

申请日：2003-02-20

Applicant: Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

Inventor： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC: H03L700

CPC classification number: H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

公开(公告)号：US06882193B2

公开(公告)日：2005-04-19

申请号：US10797253

申请日：2004-03-10

Applicant: Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

Inventor： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC: G01R19/00 ,  G01R19/155 ,  G01R19/165 ,  G06F1/28 ,  G11C5/14 ,  G11C8/08 ,  G11C11/22 ,  H03K17/22 ,  H03L7/00

CPC classification number: H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract translation: 本发明包括栅极和漏极与第一节点连接的第一MOS晶体管，栅极和漏极分别与第一节点和第三节点连接的第二MOS晶体管，第一电阻元件连接在第一节点之间 节点和第二节点，连接在第二节点和地电压端子之间的第二电阻元件，其输入端与第二节点连接的第一NOT电路，其输出端子是第四节点，并且连接在 第三节点和地电压端子，以及第二NOT电路，其输入端与第四节点连接，其输出端为第五节点。 因此，本发明能够以低功耗检测稳定状态的电压。

公开(公告)号：US06538482B2

公开(公告)日：2003-03-25

申请号：US09803775

申请日：2001-03-12

Applicant: Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

Inventor： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC: H03L700

CPC classification number: H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

公开(公告)号：US5864247A

公开(公告)日：1999-01-26

申请号：US817746

申请日：1997-07-09

Applicant: Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

Inventor： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC: G01R19/00 ,  G01R19/155 ,  G01R19/165 ,  G06F1/28 ,  G11C5/14 ,  G11C8/08 ,  G11C11/22 ,  H03K17/22

CPC classification number: H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C11/22 ,  G11C5/143 ,  G11C8/08

Abstract: The present invention includes a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract translation: PCT No.PCT / JP96 / 02295 371日期1997年7月9日第 102（e）1997年7月9日PCT PCT 1996年8月14日PCT公布。 公开号WO97 / 07408 日期：1997年02月27日本发明包括栅极和漏极与第一节点连接的第一MOS晶体管，栅极和漏极分别与第一节点和第三节点连接的第二MOS晶体管，第一电阻元件， 连接在第一节点和第二节点之间，连接在第二节点和地电压端子之间的第二电阻元件，输入端与第二节点连接的第一非电路，其输出端为第四节点， 并且其连接在第三节点和地电压端子之间，以及第二NOT电路，其输入端子与第四节点连接，并且其输出端子是第五节点。 因此，本发明能够以低功耗检测稳定状态的电压。