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    Display device
    1.
    发明授权
    Display device 有权
    显示设备

    公开(公告)号：US09147496B2

    公开(公告)日：2015-09-29

    申请号：US13486236

    申请日：2012-06-01

    申请人： Hiroyuki Abe ,  Masahiro Maki ,  Hiroaki Komatsu

    发明人： Hiroyuki Abe ,  Masahiro Maki ,  Hiroaki Komatsu

    IPC分类号： G09G3/36 ,  G11C19/28 ,  G09G3/20

    CPC分类号： G09G3/3677 ,  G09G3/20 ,  G09G3/2018 ,  G09G3/3674 ,  G09G2310/0281 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28

    摘要： A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.

    摘要翻译： 显示装置的驱动电路包括连续布置的第一至第三输出信号线，具有连接到第二输出信号线的源极和连接到第一时钟信号线的漏极的第一晶体管和提供 当第二时钟信号变为有效电位时，对第一晶体管的栅极的非有效电位，其中向第一输出信号线和第三输出信号线输出有效电位的电路设置在与第 电路，其具有介于其间的显示区域向第二输出信号线输出有效电位，并且其中第一晶体管的栅极经由整流电路连接到第一输出信号线和第三输出信号线。

    DISPLAY DEVICE
    2.
    发明申请
    DISPLAY DEVICE 有权
    显示设备

    公开(公告)号：US20120306844A1

    公开(公告)日：2012-12-06

    申请号：US13486236

    申请日：2012-06-01

    申请人： Hiroyuki ABE ,  Masahiro Maki ,  Hiroaki Komatsu

    发明人： Hiroyuki ABE ,  Masahiro Maki ,  Hiroaki Komatsu

    IPC分类号： G06F3/038

    CPC分类号： G09G3/3677 ,  G09G3/20 ,  G09G3/2018 ,  G09G3/3674 ,  G09G2310/0281 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28

    摘要： A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.

    摘要翻译： 显示装置的驱动电路包括连续布置的第一至第三输出信号线，具有连接到第二输出信号线的源极和连接到第一时钟信号线的漏极的第一晶体管和提供 当第二时钟信号变为有效电位时，对第一晶体管的栅极的非有效电位，其中向第一输出信号线和第三输出信号线输出有效电位的电路设置在与第 电路，其具有介于其间的显示区域向第二输出信号线输出有效电位，并且其中第一晶体管的栅极经由整流电路连接到第一输出信号线和第三输出信号线。

    GATE SIGNAL LINE DRIVE CIRCUIT AND DISPLAY DEVICE
    3.
    发明申请
    GATE SIGNAL LINE DRIVE CIRCUIT AND DISPLAY DEVICE 有权
    门控信号线驱动电路和显示设备

    公开(公告)号：US20120188220A1

    公开(公告)日：2012-07-26

    申请号：US13356700

    申请日：2012-01-24

    申请人： Hiroyuki ABE ,  Masahiro Maki ,  Hideo Sato ,  Hiroaki Komatsu

    发明人： Hiroyuki ABE ,  Masahiro Maki ,  Hideo Sato ,  Hiroaki Komatsu

    IPC分类号： G09G5/00

    CPC分类号： G09G3/3677 ,  G09G3/006 ,  G09G3/3611 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/0281 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2310/08

    摘要： A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.

    摘要翻译： 栅极信号线驱动电路包括多个基本电路，每个基本电路向门信号线输出在高信号周期期间为高电平的栅极信号，并在低信号周期期间输出低电平。 每个基本电路包括：玛瑙线高压施加电路，根据高信号周期接通，将高电压施加到栅极信号线; 栅极线路低电压施加电路，其根据低信号周期接通，以将低电压施加到栅极信号线; 以及第二栅极线低电压施加电路，其在关闭栅极线高压应用电路和接通栅极线路的低电压应用之间的至少一部分周期中接通以将低电压施加到栅极信号线 电路。

    Gate signal line drive circuit and display device
    4.
    发明授权
    Gate signal line drive circuit and display device 有权
    门信号线驱动电路和显示装置

    公开(公告)号：US09123274B2

    公开(公告)日：2015-09-01

    申请号：US13356700

    申请日：2012-01-24

    申请人： Hiroyuki Abe ,  Masahiro Maki ,  Hideo Sato ,  Hiroaki Komatsu

    发明人： Hiroyuki Abe ,  Masahiro Maki ,  Hideo Sato ,  Hiroaki Komatsu

    IPC分类号： G09G3/00 ,  G09G3/36

    CPC分类号： G09G3/3677 ,  G09G3/006 ,  G09G3/3611 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/0281 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2310/08

    摘要： A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.

    摘要翻译： 栅极信号线驱动电路包括多个基本电路，每个基本电路向门信号线输出在高信号周期期间为高电平的栅极信号，并在低信号周期期间输出低电平。 每个基本电路包括：玛瑙线高压施加电路，根据高信号周期接通，将高电压施加到栅极信号线; 栅极线路低电压施加电路，其根据低信号周期接通，以将低电压施加到栅极信号线; 以及第二栅极线低电压施加电路，其在关闭栅极线高压应用电路和接通栅极线路的低电压应用之间的至少一部分周期中接通以将低电压施加到栅极信号线 电路。

    Display device including a data selector circuit
    5.
    发明授权
    Display device including a data selector circuit 有权
    显示装置包括数据选择电路

    公开(公告)号：US08907993B2

    公开(公告)日：2014-12-09

    申请号：US13424540

    申请日：2012-03-20

    申请人： Hiroaki Komatsu ,  Masahiro Maki ,  Hiroyuki Abe

    发明人： Hiroaki Komatsu ,  Masahiro Maki ,  Hiroyuki Abe

    IPC分类号： G09G5/10 ,  G09G3/36

    CPC分类号： G09G3/3688 ,  G09G2310/0248 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0233

    摘要： A display device includes a plurality of gate lines, a plurality of data lines, a gate circuit, a driver, and a data selector circuit that includes a plurality of switch groups each of which has a time division switch and a timing adjustment switch that are connected in parallel. The data selector circuit outputs output signals from the driver, which have different polarities every one or more data lines of the plurality of data lines, to the respective data lines. Each of the time division switches and the timing adjustment switches is an NMOS transistor. The driver turns on the timing adjustment switches connected to the data lines to which positive output signals are output from the driver, earlier than the time division switches connected to the data lines to which negative output signals are output from the driver, by a predetermined period.

    摘要翻译： 显示装置包括多个栅极线，多条数据线，门电路，驱动器和数据选择器电路，其包括多个开关组，每个开关组具有时分开关和定时调整开关， 并联连接 数据选择器电路将来自驱动器的输出信号输出到各个数据线，每个数据线的每一条或多条数据线具有不同的极性。 每个时分开关和定时调整开关都是一个NMOS晶体管。 在连接到从驱动器输出负输出信号的数据线的时分开关之前，驱动器接通连接到从驱动器输出正输出信号的数据线的定时调整开关，预定周期 。

    INKJET PRINTING APPARATUS
    7.
    发明申请
    INKJET PRINTING APPARATUS 有权
    喷墨打印设备

    公开(公告)号：US20120026230A1

    公开(公告)日：2012-02-02

    申请号：US13188751

    申请日：2011-07-22

    申请人： Toshimitsu Danzuka ,  Kazuo Suzuki ,  Yutaka Kawamata ,  Masataka Kato ,  Asako Tomida ,  Jumpei Jogo ,  Hiroaki Komatsu

    发明人： Toshimitsu Danzuka ,  Kazuo Suzuki ,  Yutaka Kawamata ,  Masataka Kato ,  Asako Tomida ,  Jumpei Jogo ,  Hiroaki Komatsu

    IPC分类号： B41J29/38

    CPC分类号： B41J29/38 ,  B41J2/16526

    摘要： This invention prevents a possible color mixing, that may occur more than a predetermined time after the wiping operation, by executing a pre-printing cleaning ejection while at the same time minimizing the amount of waste ink produced by the cleaning ejection. To this end, if a color mixing is determined as being likely to occur an elapsed time after the previous wiping operation, the pre-printing cleaning ejection uses a second ink volume U, which represents both the color mixing elimination ink volume and the ejection failure elimination ink volume. If it is decided that there is no likelihood of the color mixing occurring the elapsed time after the wiping operation, the pre-printing cleaning ejection uses the first ink volume D which represents only the ejection failure elimination ink volume.

    摘要翻译： 本发明通过执行预打印清洁喷射来防止可能在擦拭操作之后的预定时间内发生的可能的颜色混合，同时使由清洁喷射产生的废墨的量最小化。 为此，如果将颜色混合确定为可能在先前擦拭操作之后经过的时间发生，则预打印清洁喷射使用第二墨水量U，其表示混色消除墨量和喷射失败 清除墨水量。 如果确定在擦拭操作之后经过的时间不存在颜色混合的可能性，则预打印清洁喷射使用仅表示喷射故障消除墨水量的第一墨水量D。

    INKJET APPARATUS AND METHOD OF JUDGING REPLACEMENT TIMING FOR COMPONENTS OF THE APPARATUS
    8.
    发明申请
    INKJET APPARATUS AND METHOD OF JUDGING REPLACEMENT TIMING FOR COMPONENTS OF THE APPARATUS 有权
    喷墨设备和设备组件的更换时间的方法

    公开(公告)号：US20110310159A1

    公开(公告)日：2011-12-22

    申请号：US13160787

    申请日：2011-06-15

    申请人： Kazuo Suzuki ,  Yutaka Kawamata ,  Toshimitsu Danzuka ,  Masataka Kato ,  Asako Tomida ,  Jumpei Jogo ,  Hiroaki Komatsu

    发明人： Kazuo Suzuki ,  Yutaka Kawamata ,  Toshimitsu Danzuka ,  Masataka Kato ,  Asako Tomida ,  Jumpei Jogo ,  Hiroaki Komatsu

    IPC分类号： B41J29/393

    CPC分类号： B41J29/38 ,  B41J2002/17569

    摘要： In an inkjet apparatus using an inkjet head ejecting multiple types of inks different in viscosity after evaporation of solvent, a replacement timing for a component is judged by using a consumption amount of each type of ink and a generation rate in amount of ink droplets. Accordingly, in the case of using a large amount of ink strongly susceptible to fixed adhesion and increase in viscosity, the component is replaced at an earlier timing, which prevents fixed adhesion from influencing the print performance and the printing apparatus main body. By contrast, in the case of using a large amount of ink less susceptible to fixed adhesion and increase in viscosity, the component is replaced at a later timing and thus can be used until reaching its lifetime.

    摘要翻译： 在使用喷墨头的喷墨装置中，喷射蒸发溶剂后粘度不同的多种油墨，通过使用各种油墨的消耗量和墨滴量的产生速率判断组分的更换时机。 因此，在使用大量易于固定粘附和增加粘度的油墨的情况下，更早地更换部件，这防止固定粘合剂影响打印性能和打印装置主体。 相比之下，在使用大量不易固定附着力和粘度增加的油墨的情况下，在稍后的时间更换部件，因此可以使用直到达到其使用寿命。

    Electronic tuning block
    9.
    发明授权
    Electronic tuning block 失效
    电子调音块

    公开(公告)号：US4439749A

    公开(公告)日：1984-03-27

    申请号：US363471

    申请日：1982-03-30

    申请人： Hiroaki Komatsu ,  Kenji Yoshioka

    发明人： Hiroaki Komatsu ,  Kenji Yoshioka

    IPC分类号： H05B37/03 ,  H03J1/06 ,  H03J1/08

    CPC分类号： H03J1/066

    摘要： An electronic tuning block including a plurality of screw drive type variable resistors are juxtaposed parallel to one another obliquely on an insulating substrate, and holes for receiving pointers fitted to the screws of the variable resistors and holes for receiving rotary knobs fitted to the tips of the screw shaft are formed on the upper surface of a box-shaped insulating case which is fixed to the insulating substrate.

    摘要翻译： 包括多个螺旋驱动型可变电阻器的电子调谐块在绝缘基板上倾斜地并排并置，并且用于接收安装在可变电阻器和孔的螺钉上的指针的孔，用于接收安装到 螺钉轴形成在固定在绝缘基板上的箱形绝缘壳体的上表面上。