Display Substrate and Preparation Method thereof, and Display Apparatus

    公开(公告)号:US20220115483A1

    公开(公告)日:2022-04-14

    申请号:US17266085

    申请日:2020-05-15

    Abstract: Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a plurality of display units. The display unit includes a display area and a transparent area. The display area includes a plurality of sub-pixels. In a direction perpendicular to the display substrate, the sub-pixel includes a first metal layer, a semiconductor layer, a second metal layer and a third metal layer which are arranged on a substrate. The first metal layer includes a first plate, the semiconductor layer includes a second plate, the second metal layer includes a first scanning line and a second scanning line, and the third metal layer includes a third plate, a first power supply line, a second power supply line, a compensation line and a data line.

    SHIFT REGISTER AND METHOD FOR DRIVING THE SAME, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

    公开(公告)号:US20210134203A1

    公开(公告)日:2021-05-06

    申请号:US16839858

    申请日:2020-04-03

    Abstract: A shift register, a method for driving the same, a gate driving circuit and a display device are provided. The shift register includes an input sub-circuit, an output sub-circuit, a reset sub-circuit, and a first shift output sub-circuit to an m-th shift output sub-circuit. The i-th shift output sub-circuit is connected with a third node, an (i−1)-th shift node, an i-th shift node, an (i+1)-th clock signal terminal, a first power terminal, a second power terminal, an (i−1)-th shift signal output terminal and an i-th shift signal output terminal, and is configured to supply a signal of the first power terminal to the i-th shift signal output terminal and a signal of the second power terminal to the (i−1)-th shift signal output terminal and the (i−1)-th shift node under control of the (i+1)-th clock signal terminal, i being an integer between 2 and m.

    SHIFT REGISTER AND METHOD FOR DRIVING THE SAME, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

    公开(公告)号:US20210118347A1

    公开(公告)日:2021-04-22

    申请号:US16840152

    申请日:2020-04-03

    Abstract: A shift register, a method for driving the same, a gate driving circuit and a display device are provided. The shift register includes an input sub-circuit, a pull-down control sub-circuit, an output sub-circuit and a reset sub-circuit. The pull-down control sub-circuit is connected to a first signal input terminal, a pull-up node, a pull-down node and a first power terminal, and is configured to supply a first voltage signal of the first power terminal to the pull-down node under the control of the first input signal and a potential of the pull-up node. The output sub-circuit is connected to the first node and a second clock signal terminal, and is configured to output a second clock signal of the second clock signal terminal to a first output terminal and a second output terminal under the control of the potential of the pull-up node.

    DISPLAY SUBSTRATE AND DISPLAY DEVICE
    10.
    发明申请

    公开(公告)号:US20190333943A1

    公开(公告)日:2019-10-31

    申请号:US16319704

    申请日:2018-05-11

    Abstract: A display substrate and a display device. The display substrate includes a signal line, an electro-static lead-out line, and an electro-static discharge unit including a first thin film transistor, a third thin film transistor and a fourth thin film transistor; a drain electrode and a gate electrode of the first thin film transistor are connected to the signal line; a source electrode of the first thin film transistor, a gate electrode of the third thin film transistor and a gate electrode of the fourth thin film transistor are connected to a first node; a drain electrode of the third thin film transistor and a drain electrode of the fourth thin film transistor are connected to the signal line; a source electrode of the third thin film transistor and a source electrode of the fourth thin film transistor are connected to the electro-static lead-out line.

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