Server network interface card-located baseboard management controllers

    公开(公告)号:US11927999B2

    公开(公告)日:2024-03-12

    申请号:US17450860

    申请日:2021-10-14

    CPC classification number: G06F1/26 G06F13/4221 G06F2213/0026

    Abstract: A process includes an application layer of a host of a computer platform using a smart network interface card (NIC) of the computer platform to provide an input/output (I/O) service for the application layer. The I/O service includes a service that is associated with a cloud operator domain; the smart NIC is installed in a connector; and the application layers associated with a cloud tenant domain. The process includes a baseboard management controller of the smart NIC managing the computer platform. Managing the computer platform includes the baseboard management controller managing the host; the baseboard management controller managing components of the smart NIC other than the baseboard management controller; and managing the host includes the baseboard management controller communicating with the host via the connector to control a system power state of the computer platform.

    COMMUNICATING MANAGEMENT TRAFFIC BETWEEN BASEBOARD MANAGEMENT CONTROLLERS AND NETWORK INTERFACE CONTROLLERS

    公开(公告)号:US20230134197A1

    公开(公告)日:2023-05-04

    申请号:US17452823

    申请日:2021-10-29

    Abstract: A process includes a port of a bridge providing a reference clock signal to a first end of an interconnect extending between the first port and a network interface controller. The reference clock signal propagates over the interconnect to provide, at a second end of the interconnect, a delayed reference clock signal at the network interface controller. Pursuant to the process, the bridge senses a timing of the delayed reference clock signal. The process includes communicating management traffic between a network interface of a baseboard management controller and the network interface controller via the interconnect. The communication of the management traffic includes the port, responsive to the sensing of the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the interconnect to the delayed reference clock signal.

    Securing a Memory Drive
    6.
    发明申请

    公开(公告)号:US20200257460A1

    公开(公告)日:2020-08-13

    申请号:US16429288

    申请日:2019-06-03

    Abstract: An arrangement for securing a memory device of a computing system in which a memory access command is compared to each command in a list of commands. The command, with specified attributes, is authenticated when the command and its attributes match an entry in the list of commands. Following authentication, the command is evaluated according to usage and behavior metrics in order to identify and prevent unauthorized or malicious access of the memory device. If no violation of usage or behavior metrics is detected, the command may be issued to the memory device for execution.

    SERVER NODE SHUTDOWN
    7.
    发明申请

    公开(公告)号:US20180253131A1

    公开(公告)日:2018-09-06

    申请号:US15760617

    申请日:2015-09-21

    Abstract: Example implementations relate to a server node shutdown. For example, a system includes a control module and a secondary power supply. The control module includes a detect engine to detect an even that triggers a sequenced shutdown of a server node and prevent execution of the sequenced shutdown and execution of a data transfer. The control module also includes an initiate engine to initiate a data backup process, by a basic input/output system (BIOS) of the server node, to write data from a volatile memory location of the server node to a non-volatile memory location of the server node. The secondary power supply is to support the data backup process.

    INPUT/OUTPUT EXPANSION EMULATION WITH A PROGRAMMABLE DEVICE

    公开(公告)号:US20240070092A1

    公开(公告)日:2024-02-29

    申请号:US17822702

    申请日:2022-08-26

    CPC classification number: G06F13/105 G06F13/4221 G06F2213/0026

    Abstract: In some examples, a system includes a processor, a management controller; and a programmable device to provide input/output (I/O) expansion emulation to support communication with a plurality of I/O devices of a subsystem coupled to the system, where the programmable device provides a plurality of virtual registers as part of the I/O expansion emulation, the virtual registers associated with respective I/O devices of the plurality of I/O devices. The processor writes a value to a first virtual register of the plurality of virtual registers to trigger an output event relating to a first I/O device of the plurality of I/O devices at the subsystem. The management controller reads the first virtual register and, in response to the value written to the first virtual register, interact with the subsystem to issue the output event relating to the first I/O device at the subsystem.

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