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公开(公告)号:US11927999B2
公开(公告)日:2024-03-12
申请号:US17450860
申请日:2021-10-14
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Scott P. Faasse , David F. Heinrich
CPC classification number: G06F1/26 , G06F13/4221 , G06F2213/0026
Abstract: A process includes an application layer of a host of a computer platform using a smart network interface card (NIC) of the computer platform to provide an input/output (I/O) service for the application layer. The I/O service includes a service that is associated with a cloud operator domain; the smart NIC is installed in a connector; and the application layers associated with a cloud tenant domain. The process includes a baseboard management controller of the smart NIC managing the computer platform. Managing the computer platform includes the baseboard management controller managing the host; the baseboard management controller managing components of the smart NIC other than the baseboard management controller; and managing the host includes the baseboard management controller communicating with the host via the connector to control a system power state of the computer platform.
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公开(公告)号:US20230134324A1
公开(公告)日:2023-05-04
申请号:US17452722
申请日:2021-10-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Theodore F. Emerson , Shiva R. Dasari , Luis E. Luciani, JR. , Kevin E. Boyum , Naysen J. Robertson , Robert L. Noonan , Christopher M. Wesneski , David F. Heinrich
Abstract: An apparatus includes a host and a baseboard management controller. The baseboard management controller includes a semiconductor package; and the semiconductor package includes a memory, a security hardware processor; and a main hardware processor. The main hardware processor causes the baseboard management controller to serve as an agent that, independently from the host, responds to communications with a remote management entity to manage the host. The security hardware processor manages the storage of a secret of the host in the memory.
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公开(公告)号:US20230134197A1
公开(公告)日:2023-05-04
申请号:US17452823
申请日:2021-10-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: David F. Heinrich , Gennadiy Rozenberg , Scott P. Faasse , Melvin K. Benedict
IPC: H04L7/00
Abstract: A process includes a port of a bridge providing a reference clock signal to a first end of an interconnect extending between the first port and a network interface controller. The reference clock signal propagates over the interconnect to provide, at a second end of the interconnect, a delayed reference clock signal at the network interface controller. Pursuant to the process, the bridge senses a timing of the delayed reference clock signal. The process includes communicating management traffic between a network interface of a baseboard management controller and the network interface controller via the interconnect. The communication of the management traffic includes the port, responsive to the sensing of the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the interconnect to the delayed reference clock signal.
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公开(公告)号:US10474606B2
公开(公告)日:2019-11-12
申请号:US15436015
申请日:2017-02-17
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Theodore F. Emerson , David F. Heinrich , Richard Wei Chieh Yu , Robert L. Noonan , Christopher J. Frantz , Sze Hau Loh
Abstract: Various examples described herein provide for a management controller that includes a virtual universal serial bus (USB) host controller that can emulate an actual USB host controller to a central processor. A particular endpoint from a number of endpoints is associated with a virtual USB device that is coupled to the virtual USB host controller. The particular endpoint is to refer to a location in a management memory.
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公开(公告)号:US11074199B2
公开(公告)日:2021-07-27
申请号:US15774463
申请日:2016-01-27
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: David F. Heinrich , Theodore F. Emerson , Don A. Dykes , Sukhamoy Som
Abstract: Some examples described relate to securing a memory device of a computing system. For instance, a method may comprise comparing a command for the memory device to each command in a list of commands. The command is accepted when the command matches an authorized command in the list of commands. The accepted command is issued to the memory device.
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公开(公告)号:US20200257460A1
公开(公告)日:2020-08-13
申请号:US16429288
申请日:2019-06-03
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Sukhamoy Som , David F. Heinrich , Theodore F. Emerson
Abstract: An arrangement for securing a memory device of a computing system in which a memory access command is compared to each command in a list of commands. The command, with specified attributes, is authenticated when the command and its attributes match an entry in the list of commands. Following authentication, the command is evaluated according to usage and behavior metrics in order to identify and prevent unauthorized or malicious access of the memory device. If no violation of usage or behavior metrics is detected, the command may be issued to the memory device for execution.
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公开(公告)号:US20180253131A1
公开(公告)日:2018-09-06
申请号:US15760617
申请日:2015-09-21
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: David F. Heinrich , David W. Engler , Patrick Raymond , William C. Hallowell
IPC: G06F1/26 , G06F1/30 , G06F12/0804 , G06F11/10
Abstract: Example implementations relate to a server node shutdown. For example, a system includes a control module and a secondary power supply. The control module includes a detect engine to detect an even that triggers a sequenced shutdown of a server node and prevent execution of the sequenced shutdown and execution of a data transfer. The control module also includes an initiate engine to initiate a data backup process, by a basic input/output system (BIOS) of the server node, to write data from a volatile memory location of the server node to a non-volatile memory location of the server node. The secondary power supply is to support the data backup process.
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公开(公告)号:US20180074777A1
公开(公告)日:2018-03-15
申请号:US15565225
申请日:2015-05-21
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Theodore F. Emerson , David F. Heinrich , Kenneth T. Chin
IPC: G06F3/14 , H04N21/2365 , H04N21/242 , G06T1/60
CPC classification number: G06F3/1438 , G06T1/60 , G09G2352/00 , G09G2360/12 , G09G2370/24 , H04N5/76 , H04N21/2365 , H04N21/242 , H04N21/42653
Abstract: An apparatus includes a plurality of compute nodes and a baseboard management controller that is shared by the plurality of compute nodes to manage video for the compute nodes. The baseboard management controller includes video controllers that are associated with the plurality of compute nodes and at least one resource that is shared by the video controllers.
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公开(公告)号:US12105643B2
公开(公告)日:2024-10-01
申请号:US17355833
申请日:2021-06-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor: David F. Heinrich , Theodore F. Emerson , Don A. Dykes , Sukhamoy Som
CPC classification number: G06F12/1416 , G06F3/0622 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F21/00 , G06F21/85 , G06F2212/1052 , G06F2212/7207 , G06F2212/7209
Abstract: Some examples described relate to securing a memory device of a computing system. For instance, a method may comprise comparing a command for the memory device to each command in a list of commands. The command is accepted when the command matches an authorized command in the list of commands. The accepted command is issued to the memory device.
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公开(公告)号:US20240070092A1
公开(公告)日:2024-02-29
申请号:US17822702
申请日:2022-08-26
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Binh Q. Nguyen , David F. Heinrich , Paul Anthony Kaler
CPC classification number: G06F13/105 , G06F13/4221 , G06F2213/0026
Abstract: In some examples, a system includes a processor, a management controller; and a programmable device to provide input/output (I/O) expansion emulation to support communication with a plurality of I/O devices of a subsystem coupled to the system, where the programmable device provides a plurality of virtual registers as part of the I/O expansion emulation, the virtual registers associated with respective I/O devices of the plurality of I/O devices. The processor writes a value to a first virtual register of the plurality of virtual registers to trigger an output event relating to a first I/O device of the plurality of I/O devices at the subsystem. The management controller reads the first virtual register and, in response to the value written to the first virtual register, interact with the subsystem to issue the output event relating to the first I/O device at the subsystem.
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