公开(公告)号：US09158688B1

公开(公告)日：2015-10-13

申请号：US14182579

申请日：2014-02-18

Applicant: Google Inc.

Inventor： Dennis C. Abts ,  Daniel Gibson

IPC: G06F15/18 ,  G06F12/08 ,  G06F17/50

CPC classification number: G06F12/0813 ,  G06F15/17312 ,  G06F17/5072 ,  G06F17/5077

Abstract: The location of the memory controllers within the on-chip fabric of multiprocessor architectures plays a central role in latency bandwidth characteristics of the processor-to-memory traffic. Intelligent placement substantially reduces the maximum channel load depending on the specific memory controller configuration selected. A variety of simulation techniques are used along and in combination to determine optimal memory controller arrangements. Diamond-type and diagonal X-type memory controller configurations that spread network traffic across all rows and columns in a multiprocessor array substantially improve over other arrangements. Such placements reduce interconnect latency by an average of 10% for real workloads, and the small number of memory controllers relative to the number of on-chip cores opens up a rich design space to optimize latency and bandwidth characteristics of the on-chip network.

Abstract translation: 多处理器架构的片上架构内的存储器控​​制器的位置在处理器到存储器流量的延迟带宽特性中起着核心作用。 根据所选择的特定内存控制器配置，智能放置可显着降低最大通道负载。 各种模拟技术沿着并结合使用以确定最佳的存储器控​​制器布置。 在多处理器阵列中跨所有行和列传播网络流量的钻石型和对角X型存储器控制器配置大大改进了其他布置。 这样的布局将实际工作负载的互连延迟平均降低了10％，而相对于片上内核数量的少量内存控制器开辟了丰富的设计空间，以优化片上网络的延迟和带宽特性。

公开(公告)号：US09391871B1

公开(公告)日：2016-07-12

申请号：US14254996

申请日：2014-04-17

Applicant: Google Inc.

Inventor： Dennis C. Abts ,  Michael Marty

IPC: H04L12/26 ,  H04L1/00 ,  H04J3/14 ,  H04L12/733 ,  H04L12/70

CPC classification number: H04L45/122 ,  H04L47/10 ,  H04L49/109 ,  H04L2012/5678 ,  H04L2012/5679 ,  H04W84/18

Abstract: Probabilistic arbitration is combined with distance-based weights to achieve equality of service in interconnection networks, such as those used with chip multiprocessors. This arbitration desirably used incorporates nonlinear weights that are assigned to requests. The nonlinear weights incorporate different arbitration weight metrics, namely fixed weight, constantly increasing weight, and variably increasing weight. Probabilistic arbitration for an on-chip router avoids the need for additional buffers or virtual channels, creating a simple, low-cost mechanism for achieving equality of service. The nonlinearly weighted probabilistic arbitration includes additional benefits such as providing quality-of-service features and fairness in terms of both throughput and latency that approaches the global fairness achieved with age-base arbitration. This provides a more stable network by achieving high sustained throughput beyond saturation. Each router or switch in the network may include an arbiter to apply the weighted probabilistic arbitration.

Abstract translation: 概率仲裁与基于距离的权重相结合，以实现互连网络中的服务等同，如与芯片多处理器一起使用的。 期望使用的仲裁包括分配给请求的非线性权重。 非线性权重包含不同的仲裁权重度量，即固定权重，不断增加的权重和可变增加权重。 片上路由器的概率仲裁避免了对附加缓冲区或虚拟通道的需求，创建了一种实现平等服务的简单，低成本的机制。 非线性加权概率仲裁包括额外的好处，例如提供服务质量特征和在通过年龄基础仲裁实现的全球公平的吞吐量和延迟方面的公平性。 这通过实现高饱和度的高持续吞吐量来提供更稳定的网络。 网络中的每个路由器或交换机可以包括应用加权概率仲裁的仲裁器。