公开(公告)号：US09952875B2

公开(公告)日：2018-04-24

申请号：US12609193

申请日：2009-10-30

Applicant: Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

Inventor： Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

IPC: G06F9/312 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3875 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3893 ,  G06F12/0875

Abstract: A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and distinct from the other execution units of the microprocessor. The store unit comprises an ALU. The store unit receives an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result. The store unit reads the source operand from the source register. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The store unit operatively writes the result to the cache memory.

公开(公告)号：US20140122847A1

公开(公告)日：2014-05-01

申请号：US14007116

申请日：2012-04-06

Applicant: G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC: G06F9/26

CPC classification number: G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

Abstract: An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.

Abstract translation: 指令转换器接收指定条件，目标/数据寄存器，基址寄存器，偏移源和存储器寻址模式的条件加载/存储指令。 只有当条件标志满足条件时，指令才指示微处理器将数据从存储单元加载到目标寄存器（条件加载）中，或者将数据从数据寄存器（条件存储）​​存储到存储单元。 偏移源指定偏移量是立即值还是偏移量寄存器中的值。 寻址模式指定条件标志满足条件时是否更新基址寄存器。 指令翻译器将条件加载指令转换为多个微指令，其作为偏移源，寻址模式以及条件指令是条件加载还是存储指令的函数而变化。 无序执行流水线执行微指令以生成指令指定的结果。

公开(公告)号：US20110035569A1

公开(公告)日：2011-02-10

申请号：US12609169

申请日：2009-10-30

Applicant: Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

Inventor： Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

IPC: G06F9/30 ,  G06F12/08 ,  G06F9/302 ,  G06F9/305

CPC classification number: G06F9/3875 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3893 ,  G06F12/0875

Abstract: A superscalar pipelined microprocessor includes a register set defined by its instruction set architecture, a cache memory, execution units, and a load unit, coupled to the cache memory and distinct from the other execution units. The load unit comprises an ALU. The load unit receives an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored. The load unit reads the source operand from the cache memory. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The load unit outputs the result for subsequent retirement to the destination register.

Abstract translation: 超标量流水线微处理器包括由其指令集架构定义的寄存器组，高速缓冲存储器，执行单元和负载单元，耦合到高速缓冲存储器并且与其他执行单元不同。 负载单元包括一个ALU。 加载单元接收指定源操作数的存储器地址的指令，要在源操作数上执行的用于生成结果的操作以及要存储结果的寄存器集的目标寄存器。 加载单元从缓存中读取源操作数。 ALU对源操作数执行操作以生成结果，而不是将源操作数转发到微处理器的任何其他执行单元，以对源操作数执行操作以生成结果。 加载单元将结果退出到目的地寄存器。

公开(公告)号：US09501286B2

公开(公告)日：2016-11-22

申请号：US12609169

申请日：2009-10-30

Applicant: Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

Inventor： Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3875 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3893 ,  G06F12/0875

Abstract: A superscalar pipelined microprocessor includes a register set defined by its instruction set architecture, a cache memory, execution units, and a load unit, coupled to the cache memory and distinct from the other execution units. The load unit comprises an ALU. The load unit receives an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored. The load unit reads the source operand from the cache memory. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The load unit outputs the result for subsequent retirement to the destination register.

Abstract translation: 超标量流水线微处理器包括由其指令集架构定义的寄存器组，高速缓冲存储器，执行单元和负载单元，耦合到高速缓冲存储器并且与其他执行单元不同。 负载单元包括一个ALU。 加载单元接收指定源操作数的存储器地址的指令，要在源操作数上执行的用于生成结果的操作以及要存储结果的寄存器集的目标寄存器。 加载单元从缓存中读取源操作数。 ALU对源操作数执行操作以生成结果，而不是将源操作数转发到微处理器的任何其他执行单元，以对源操作数执行操作以生成结果。 加载单元将结果退出到目的地寄存器。

公开(公告)号：US09244686B2

公开(公告)日：2016-01-26

申请号：US14007116

申请日：2012-04-06

Applicant: G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/26 ,  G06F9/38 ,  G06F15/82

CPC classification number: G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

Abstract: An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.

Abstract translation: 指令转换器接收指定条件，目标/数据寄存器，基址寄存器，偏移源和存储器寻址模式的条件加载/存储指令。 只有当条件标志满足条件时，指令才指示微处理器将数据从存储单元加载到目标寄存器（条件加载）中，或者将数据从数据寄存器（条件存储）​​存储到存储单元。 偏移源指定偏移量是立即值还是偏移量寄存器中的值。 寻址模式指定条件标志满足条件时是否更新基址寄存器。 指令翻译器将条件加载指令转换为多个微指令，其作为偏移源，寻址模式以及条件指令是条件加载还是存储指令的函数而变化。 无序执行流水线执行微指令以生成指令指定的结果。

公开(公告)号：US20110035570A1

公开(公告)日：2011-02-10

申请号：US12609193

申请日：2009-10-30

Applicant: Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

Inventor： Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

IPC: G06F9/30 ,  G06F12/08 ,  G06F9/302 ,  G06F9/305

CPC classification number: G06F9/3875 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3893 ,  G06F12/0875

Abstract: A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and distinct from the other execution units of the microprocessor. The store unit comprises an ALU. The store unit receives an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result. The store unit reads the source operand from the source register. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The store unit operatively writes the result to the cache memory.

Abstract translation: 超标量流水线微处理器包括由微处理器的指令集架构定义的寄存器组，执行单元和存储单元，其耦合到高速缓冲存储器并且与微处理器的其他执行单元不同。 存储单元包括ALU。 存储单元接收指定寄存器组的源寄存器和要对源操作数执行的操作以产生结果的指令。 存储单元从源寄存器读取源操作数。 ALU对源操作数执行操作以生成结果，而不是将源操作数转发到微处理器的任何其他执行单元，以对源操作数执行操作以生成结果。 存储单元可操作地将结果写入缓存存储器。

公开(公告)号：US20090204800A1

公开(公告)日：2009-08-13

申请号：US12100616

申请日：2008-04-10

Applicant: Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

Inventor： Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC: G06F9/22

CPC classification number: G06F9/3004 ,  G06F9/30087 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855

Abstract: The microprocessor includes an instruction translator that translates a macroinstruction of a macroinstruction set in its macroarchitecture into exactly three microinstructions to perform a read/modify/write operation on a memory operand. The first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to calculate a destination address of the memory location. The second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result. The third microinstruction instructs the microprocessor to write the result to the memory location whose destination address is calculated by the first microinstruction. A first execution unit receives the first microinstruction and responsively loads the memory operand into the microprocessor from the memory location, and a second distinct execution unit also receives the first microinstruction and responsively calculates the destination address of the memory location.

Abstract translation: 微处理器包括一个指令转换器，它将宏构造中的宏指令集的宏指令转换成三个微指令，以对存储器操作数执行读/修/写操作。 第一微指令指示微处理器从存储器位置将存储器操作数加载到微处理器中并计算存储器位置的目的地地址。 第二微指令指示微处理器对加载的存储器操作数执行算术或逻辑运算以产生结果。 第三个微指令指示微处理器将结果写入由第一个微指令计算目标地址的存储单元。 第一执行单元接收第一微指令并且响应地将存储器操作数从存储器位置加载到微处理器中，并且第二不同执行单元还接收第一微指令并且响应地计算存储器位置的目的地地址。

公开(公告)号：US09645822B2

公开(公告)日：2017-05-09

申请号：US14007097

申请日：2012-04-06

Applicant: G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC: G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30076 ,  G06F9/30123 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196

Abstract: An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.

公开(公告)号：US20140122843A1

公开(公告)日：2014-05-01

申请号：US14007097

申请日：2012-04-06

Applicant: G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30076 ,  G06F9/30123 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196

Abstract: An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.

Abstract translation: 指令翻译器将条件存储指令（指定寄存器文件的指定数据寄存器，基址寄存器和偏移寄存器）转换为至少两个微指令。 无序执行管线执行微指令。 为了执行第一微指令，执行单元从寄存器文件接收基值和偏移量，并且产生作为基值和偏移量的函数的第一结果。 第一个结果指定内存位置地址。 为了执行第二微指令，如果条件标志满足条件（存储队列随后将数据写入由地址指定的存储器位置），则执行单元接收第一结果并将第一结果写入存储队列中的已分配条目， ，否则将杀死所分配的存储队列条目，使得存储队列不将数据写入由地址指定的存储器位置。

公开(公告)号：US08069340B2

公开(公告)日：2011-11-29

申请号：US12100616

申请日：2008-04-10

Applicant: Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

Inventor： Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30087 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855

Abstract: A microprocessor instruction translator translates a macroinstruction into three microinstructions to perform a read/modify/write operation on a memory operand. A first microinstruction instructs the microprocessor to calculate a source address and to load the memory operand into the microprocessor from memory at the source address and to calculate a destination address. The second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result. The third microinstruction instructs the microprocessor to write the result to memory at the destination address calculated by the first microinstruction. A first execution unit receives the first microinstruction and responsively calculates the source address and loads the memory operand into the microprocessor from memory at the source address. A second execution unit also receives the first microinstruction and calculates the destination address. The first and second execution units are distinct execution units within the microprocessor.

Abstract translation: 微处理器指令转换器将宏指令转换成三个微指令以对存储器操作数执行读/修改/写操作。 第一微指令指示微处理器计算源地址，并将存储器操作数从源地址的存储器加载到微处理器中并计算目的地地址。 第二微指令指示微处理器对加载的存储器操作数执行算术或逻辑运算以产生结果。 第三个微指令指示微处理器将结果写入由第一个微指令计算的目标地址的存储器。 第一执行单元接收第一微指令并且响应地计算源地址并且将来自地址的存储器的存储器操作数加载到微处理器中。 第二执行单元还接收第一微指令并计算目的地址。 第一和第二执行单元是微处理器内不同的执行单元。