Abstract:
A gun includes a frame and a pivoting barrel assembly which is releasably latched in a firing position by a pair of flexible and resilient latches on the barrel assembly which engage shoulders on the frame. A trigger is slidably mounted on the frame for movement between a rest position and a firing position. A projectile loader is mounted on the frame at the breech end of the barrel assembly for movement between a loading position and a firing position. The loader is provided with an opening which is aligned with a magazine in the frame when the loader is in the loading position and is aligned with the bore of the barrel assembly when the loader is in the firing position. A camming ramp on the trigger is engageable with the loader for moving the loader between the loading and firing positions as the trigger moves between the rest and firing positions. A trigger interlock is movably mounted on the frame and engages the trigger when the barrel assembly is out of the firing position for preventing the trigger from moving to the firing position. The trigger interlock is moved out of engagement with the trigger by the barrel assembly when the barrel assembly moves to the firing position.
Abstract:
A chewing tobacco preserving assembly for preserving freshness of chewing tobacco includes a tobacco can which contains chewing tobacco. A canister is provided for insertably receiving the tobacco can. The canister is thermally insulated thereby inhibiting the tobacco can from being in thermal communication with ambient air for preserving freshness of the chewing tobacco. A lid is removably attachable to the canister for enclosing the tobacco can in the canister.
Abstract:
Transmitter-based techniques are provided for compensation of intersymbol interference and/or simultaneous switching outputs, using selective pulse width modulation. One or more signals are transmitted by detecting whether one or more of said signals satisfy one or more predefined signal corruption conditions, wherein said predefined signal corruption conditions indicate that one or more of said signals are anticipated to exhibit one or more of intersymbol interference and simultaneous switching outputs; and selecting a delay for one or more of the signals based on the one or more predefined signal corruptions conditions. The predefined signal corruption conditions comprise, for example, (i) digital data encoded in the one or more signals maintaining a same binary value for two or more consecutive clock cycles (to indicate intersymbol interference); and (ii) a predefined minimum number of aggressor data edges in digital data encoded in the one or more signals, and a corresponding predefined number of victim data edges in the digital data encoded in the one or more signals, wherein the victim edges are moving in an opposite direction to the aggressor data edges (to indicate simultaneous switching outputs).
Abstract:
A tool reduces a flow of liquid or gas through a conduit. The tool includes a crimping section having a first crimping member with a first blunt section extending partially along an edge thereof and a second crimping member having a second blunt section extending partially along an edge thereof. The first and second members are pivotally engaged with one another. A handle section is connected to the crimping section. The handle section includes a first handle member connected to the first crimping member and a second handle member connected to the second crimping member. A hinge pivotally connects the first handle member to the second handle member. When the first and second handle members are pivoted about the hinge, the first and second crimping members are caused to pivot in a direction opposite to the respective first and second handle members.
Abstract:
A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
Abstract:
The present invention provides methods that utilize compositions containing colostrinin, a constituent peptide thereof, an active analog thereof, and combinations thereof, as inhibitors of apoptosis, for example.
Abstract:
The invention relates to the automatic reloading of the gas space of a hydropneumatic accumulator. An apparatus for readjusting the load of the gas space includes a pressurized gas source connected via an air system to a loading check-valve and a reinjection valve controlled by a unit for calculating a cycle for reinjecting gas into the gas space.
Abstract:
An assembly for maintaining tension in a drive belt features a housing mounted on a base. The housing contains a biasing element that exerts torque on the housing to bias the housing in a radial direction. A lever arm is connected to the housing and rotates with the housing in response to the bias of the biasing element. A pulley is connected to the lever arm and engages a drive belt in response to the bias force of the biasing element on the lever arm. The pulley deflects the shape of the belt to provide tension in the belt. In one embodiment, the apparatus allows the user to switch the position of the biasing element and alter the direction of torque on the lever arm. In another embodiment, the lever arm and pulley are removable from the housing and replaceable with other arms and pulleys having different configurations.
Abstract:
Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial write-leveling procedure determines the correct skew and programs a register file in the skew adjustment circuit. The register file includes a register for each of multiple ranks in the DDR3 memory. The values in each register serve to control selection of alignment of the data related signals to align with one of multiple phase shifted versions of a 1× DDR3 clock signal. The phase shifted clock signals are generated by clock divider circuits from a 2× DDR clock signal and use of a single fixed delay line approximating ⅛ of a 1× DDR3 clock period.
Abstract:
The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO (First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM (Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.