公开(公告)号：US10754689B1

公开(公告)日：2020-08-25

申请号：US16274685

申请日：2019-02-13

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： Shige Wang ,  Unmesh Dutta Bordoloi ,  Stephen G. Lusko ,  Stephen N. McKinnie

IPC: G06F9/48 ,  H04L12/873 ,  G06F9/38 ,  H04L29/08 ,  H04L12/865 ,  H04L12/863 ,  G06K9/00

Abstract: A stream manager for managing the distribution of instructions to a plurality of processing devices includes a dispatcher module configured to: receive multiple instruction streams, wherein each instruction stream includes a plurality of requested computations for processing perception data from a perception data source; partition each instruction stream into a plurality of partitions based on type of device to perform a requested computation from the instruction stream; assign a release time and deadline to each partition, and dispatch partition computations to a plurality of scheduling queues to distribute processing of the partition computations amongst the plurality of processing devices. The plurality of scheduling queues include: a plurality of CPU schedulers, wherein each CPU scheduler is assigned to a specific CPU and a specific scheduling queue; and a plurality of accelerator schedulers, wherein each accelerator scheduler is assigned to a specific scheduling queue and a specific type of accelerator.

公开(公告)号：US09775035B2

公开(公告)日：2017-09-26

申请号：US14853266

申请日：2015-09-14

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： Shige Wang ,  Stephen G. Lusko

IPC: H04L29/06 ,  H04W12/06 ,  H04L12/58 ,  H04L29/08 ,  H04L12/40

CPC classification number: H04W12/06 ,  H04L12/40013 ,  H04L51/26 ,  H04L63/08 ,  H04L67/12 ,  H04L2012/40215

Abstract: A secure messaging communication system. A communication bus communicates messages between transmitting nodes. A secure hardware engine of a controller authenticates messages from requesting entities. A processor of the controller initially receives messages from the requesting entities. The processor includes a message request queue prioritizing received messages. The processor communicates a prioritized message from the request queue and associated authentication information to the secure hardware engine. The secure hardware engine authenticates the messages in response to receiving the prioritized messages and associated authentication information from the processor. The secure hardware engine communicates the authenticated messages to the processor for storage in a results queue.

公开(公告)号：US10686988B2

公开(公告)日：2020-06-16

申请号：US15950587

申请日：2018-04-11

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： Unmesh Dutta Bordoloi ,  Shige Wang ,  Stephen G. Lusko ,  Jinsong Wang

IPC: H04N5/232 ,  G06N3/04 ,  B60R1/00

Abstract: Examples of techniques for dynamically selecting a batch size used in vehicle camera image processing are disclosed. In one example implementation, a method includes generating, by a processing device, a batch table and a mode table. The method further includes determining, by the processing device, image processing performance requirements for a current mode of a vehicle using the mode table, the vehicle comprising a plurality of cameras configured to capture a plurality of images. The method further includes selecting, by the processing device, a batch size and a processing frequency based at least in part on the image processing performance requirements for the current mode of the vehicle. The method further includes processing, by an accelerator, at least a subset of the plurality of images based at least in part on the batch size and processing frequency.

公开(公告)号：US09830270B2

公开(公告)日：2017-11-28

申请号：US14951656

申请日：2015-11-25

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： Shuqing Zeng ,  Shige Wang ,  Stephen G. Lusko

IPC: G06F12/08 ,  G06F12/0868

CPC classification number: G06F12/0868 ,  G06F9/00 ,  G06F9/30 ,  G06F2212/1008 ,  G06F2212/281 ,  G06F2212/452

Abstract: A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted in the global memory device. Memory access traces relating to executed tasks are accessed from the signal list. Memory locations accessed in the global memory device from the access traces are identified. A correlation value for each pair of memory locations accessed in the global memory device is determined. Correlation values of the pairs of memory locations are determined, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations. Accessed memory locations within the global memory device are reordered as a function of the determined correlation values. An executable file accessing the global memory device is modified.

公开(公告)号：US20200257560A1

公开(公告)日：2020-08-13

申请号：US16274685

申请日：2019-02-13

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： Shige Wang ,  Unmesh Dutta Bordoloi ,  Stephen G. Lusko ,  Stephen N. McKinnie

IPC: G06F9/48 ,  G06F9/38 ,  H04L12/863 ,  H04L12/865 ,  H04L12/873 ,  H04L29/08

Abstract: A stream manager for managing the distribution of instructions to a plurality of processing devices includes a dispatcher module configured to: receive multiple instruction streams, wherein each instruction stream includes a plurality of requested computations for processing perception data from a perception data source; partition each instruction stream into a plurality of partitions based on type of device to perform a requested computation from the instruction stream; assign a release time and deadline to each partition, and dispatch partition computations to a plurality of scheduling queues to distribute processing of the partition computations amongst the plurality of processing devices. The plurality of scheduling queues include: a plurality of CPU schedulers, wherein each CPU scheduler is assigned to a specific CPU and a specific scheduling queue; and a plurality of accelerator schedulers, wherein each accelerator scheduler is assigned to a specific scheduling queue and a specific type of accelerator.

公开(公告)号：US20190320115A1

公开(公告)日：2019-10-17

申请号：US15950587

申请日：2018-04-11

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： Unmesh Dutta Bordoloi ,  Shige Wang ,  Stephen G. Lusko ,  Jinsong Wang

IPC: H04N5/232 ,  G06N3/04 ,  B60R1/00

Abstract: Examples of techniques for dynamically selecting a batch size used in vehicle camera image processing are disclosed. In one example implementation, a method includes generating, by a processing device, a batch table and a mode table. The method further includes determining, by the processing device, image processing performance requirements for a current mode of a vehicle using the mode table, the vehicle comprising a plurality of cameras configured to capture a plurality of images. The method further includes selecting, by the processing device, a batch size and a processing frequency based at least in part on the image processing performance requirements for the current mode of the vehicle. The method further includes processing, by an accelerator, at least a subset of the plurality of images based at least in part on the batch size and processing frequency.

公开(公告)号：US10360079B2

公开(公告)日：2019-07-23

申请号：US15625051

申请日：2017-06-16

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： Shige Wang ,  Stephen G. Lusko

IPC: G06F9/46 ,  G06F9/52 ,  G06F16/27

Abstract: A synchronization method in a multiprocessor system is provided. The method includes providing a plurality of synchronization mechanisms for synchronizing data to be accessed by a plurality of concurrently executable tasks, analyzing design information and runtime information for application software that includes the concurrently executable tasks, identifying, based on the analysis, software architecture patterns for the concurrently executable tasks that access a shared variable, and associating, based on the analysis, each of the software architecture patterns to one or more of the synchronization mechanisms. The method further includes generating synchronization table entries for a synchronization table that identify the shared variable, the software architecture pattern for the concurrently executable tasks that access the shared variable, and the one or more synchronization mechanisms associated with the software architecture pattern and also includes accessing the shared variable using the one or more synchronization mechanisms identified in the synchronization table.