公开(公告)号：US08879640B2

公开(公告)日：2014-11-04

申请号：US13027277

申请日：2011-02-15

Applicant: Felix Chow ,  Chun Hang Lee

Inventor： Felix Chow ,  Chun Hang Lee

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H03D1/00 ,  H04L27/06 ,  G06F21/00 ,  G06F13/00

CPC classification number: H03M13/1125 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/1515 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/2778 ,  H03M13/2792 ,  H03M13/2906 ,  H03M13/6505

Abstract: A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

Abstract translation: 一种解码低密度奇偶校验（LDPC）码的计算机可执行方法，包括：接收对数似然比（LLR）输入比特流; 对所述LLR输入比特流执行组合的比特解交织和重排序处理并存储在物理存储器空间中，包括：为所述LLR输入比特流中的每个LLR比特确定逻辑存储器地址，确定所述LLR比特中的每个LLR比特的物理存储器地址 LLR从LLR位的逻辑存储器地址输入比特流; 解码存储在物理存储器空间中的LLR输入比特流; 以及对解码的LLR输入比特流执行组合去重排序和解映射处理。

公开(公告)号：US20120207224A1

公开(公告)日：2012-08-16

申请号：US13027277

申请日：2011-02-15

Applicant: Felix Chow ,  Chun Hang Lee

Inventor： Felix Chow ,  Chun Hang Lee

IPC: H04N7/26

CPC classification number: H03M13/1125 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/1515 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/2778 ,  H03M13/2792 ,  H03M13/2906 ,  H03M13/6505

Abstract: A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

Abstract translation: 一种解码低密度奇偶校验（LDPC）码的计算机可执行方法，包括：接收对数似然比（LLR）输入比特流; 对所述LLR输入比特流执行组合的比特解交织和重排序处理并存储在物理存储器空间中，包括：为所述LLR输入比特流中的每个LLR比特确定逻辑存储器地址，确定所述LLR比特中的每个LLR比特的物理存储器地址 LLR从LLR位的逻辑存储器地址输入比特流; 解码存储在物理存储器空间中的LLR输入比特流; 以及对解码的LLR输入比特流执行组合去重排序和解映射处理。