公开(公告)号：US20180315687A1

公开(公告)日：2018-11-01

申请号：US15956829

申请日：2018-04-19

Applicant: FUJITSU LIMITED

Inventor： Kei FUKUI ,  Youichi Hoshikawa ,  Hiromitsu KOBAYASHI ,  Hidehiko Fujisaki ,  Seigo Yamawaki ,  Masateru Koide ,  MANABU WATANABE ,  Daisuke Mizutani ,  Tomoyuki AKAHOSHI

IPC: H01L23/498 ,  H05K1/16 ,  H01L49/02

CPC classification number: H01L23/49822 ,  H01L28/40 ,  H05K1/162 ,  H05K3/4632 ,  H05K3/4652 ,  H05K3/4676

Abstract: A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first surface having the first wiring pattern, a second resin layer stacked on the first resin layer, and a component fixed to the second resin layer in which a second wiring pattern formed on a second surface of the component is buried.

公开(公告)号：US20210375771A1

公开(公告)日：2021-12-02

申请号：US17177247

申请日：2021-02-17

Applicant: FUJITSU LIMITED

Inventor： KENJI FUKUZONO ,  MANABU WATANABE ,  Yuki Hoshino ,  Hiroshi Onuki

IPC: H01L23/538 ,  H01L25/18

Abstract: An electronic device includes a bus bar that includes a first terminal and a second terminal and extends between the first terminal and the second terminal on a side of a first surface of a substrate; first solder configured to pass through the substrate in a thickness direction and connect a first through terminal connected to a first electronic component that is disposed on a second surface side of the substrate and the first terminal; and second solder configured to pass through the substrate in the thickness direction and connect a second through terminal connected to a second electronic component disposed on the second surface side of the substrate and the second terminal.

公开(公告)号：US20190053385A1

公开(公告)日：2019-02-14

申请号：US16162470

申请日：2018-10-17

Applicant: FUJITSU LIMITED

Inventor： Masaharu Furuyama ,  Daisuke Mizutani ,  Tomoyuki AKAHOSHI ,  Masateru Koide ,  MANABU WATANABE ,  Seigo Yamawaki ,  Kei FUKUI

IPC: H05K3/46 ,  H01L49/02 ,  H01L23/498 ,  H01G4/33 ,  H01G4/228 ,  H05K1/16

Abstract: A circuit board includes: an insulating layer; a capacitor which is provided in the insulating layer and which includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including an opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a recess part at a position corresponding to the opening part; and a conductor via provided in the insulating layer, penetrating the dielectric layer, the opening part and the recess part, being in contact with the recess part, and being smaller than the opening part in plan view.

公开(公告)号：US20180358289A1

公开(公告)日：2018-12-13

申请号：US16001980

申请日：2018-06-07

Applicant: FUJITSU LIMITED

Inventor： MANABU WATANABE ,  KENJI FUKUZONO ,  Yuki Hoshino ,  Masateru Koide

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/49838

Abstract: A package substrate includes a substrate, a first connection terminal mounted over the substrate, the first connection terminal including a first land and a second land on the substrate, a first solder resist surrounding the first land and the second land, and a first solder ball formed straddling the first land and the second land; and a second connection terminal which is mounted over the substrate and disposed adjacent to the first connection terminal, the second connection terminal including a third land and a fourth land on the substrate, a second solder resist surrounding the third land and the fourth land, and a second solder ball formed straddling the third land and the fourth land.