公开(公告)号：US10749027B2

公开(公告)日：2020-08-18

申请号：US16234844

申请日：2018-12-28

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION

Inventor： Joseph A. Yedinak ,  Richard Stokes ,  Jason Higgs ,  Fred Session

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L21/02 ,  H01L29/739

Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.

公开(公告)号：US20190245078A1

公开(公告)日：2019-08-08

申请号：US16234844

申请日：2018-12-28

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION

Inventor： Joseph A. Yedinak ,  Richard Stokes ,  Jason Higgs ,  Fred Session

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L21/02 ,  H01L29/739 ,  H01L29/423

Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.

公开(公告)号：US09496391B2

公开(公告)日：2016-11-15

申请号：US14204765

申请日：2014-03-11

Applicant: Fairchild Semiconductor Corporation

Inventor： Joseph A. Yedinak ,  Richard Stokes ,  Jason Higgs ,  Fred Session

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/0661 ,  H01L21/02104 ,  H01L29/06 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.

Abstract translation: 在一个一般的方面，装置可以包括半导体区域和限定在半导体区域内的沟槽。 沟槽可以具有沿垂直轴线对齐的深度并且具有沿着垂直于垂直轴线的纵向轴线对准的长度。 沟槽可以具有包括在半导体区域的终止区域中的长度的第一部分，并且可以具有包括在半导体区域的有源区域中的长度的第二部分。