公开(公告)号：US20190289229A1

公开(公告)日：2019-09-19

申请号：US16356788

申请日：2019-03-18

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hyun Kyu YU ,  Sung Weon KANG ,  Young-Su KWON ,  JOO HYUN LEE

IPC: H04N5/341 ,  G06K9/46 ,  G06T7/13 ,  G06T7/246

Abstract: Provided is an image sensor. The image sensor includes a pixel array including pixels arranged along a first direction and a second direction, and partitioned into blocks, a converter configured to convert image signals outputted from the pixels into digital signals based on an image, and an image signal processor configured to add amplitudes of the digital signals belonging to each of the blocks to determine edge blocks among the blocks, compare the amplitudes of the digital signals to determine directions in which direction lines of the edge blocks are directed, and connect the direction lines to extract an edge of the image.

公开(公告)号：US20140266354A1

公开(公告)日：2014-09-18

申请号：US14028707

申请日：2013-09-17

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hyun Ho BOO ,  Byung Hun MIN ,  Duong Quoc HOANG ,  Cheon Soo KIM ,  Hyun Kyu YU

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/095

Abstract: Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.

Abstract translation: 公开了一种数字锁相环，包括：时间数字转换器（TDC），被配置为基于输入时钟和参考时钟输出数字位，其中TDC包括：第一仲裁器组，其被配置为补偿 对于具有第一平均偏移的输入时钟和参考时钟之间的相位差，并输出第一逻辑值; 第二仲裁器组，被配置为用第二平均偏移补偿所述输入时钟和所述参考时钟之间的相位差，并输出第二逻辑值; 以及信号处理器，被配置为基于第一和第二逻辑值输出数字位。

公开(公告)号：US20130178179A1

公开(公告)日：2013-07-11

申请号：US13737726

申请日：2013-01-09

Applicant: Electronics and Telecommunications Research Institute

Inventor： Seon-Ho HAN ,  Hyun Kyu YU

IPC: H04B1/06

CPC classification number: H04B1/06 ,  H04B1/0014

Abstract: The inventive concept relates to a wireless communication receiver. The wireless communication receiver includes a second off-chip RF filter, an RF-to-digital converter and a digital pre-processor processing a signal converted into a digital. The RF-to-digital converter converts an RF signal being received into a digital signal of DC frequency band or intermediate frequency band and has a dynamic range that can process a wanted RF band signal and unwanted signals near to the wanted RF band signal. The digital pre-processor digitally controls a signal gain to transmit it to a modulator/demodulator.

Abstract translation: 本发明构思涉及无线通信接收机。 无线通信接收机包括第二片外RF滤波器，RF到数字转换器和处理转换成数字信号的数字预处理器。 RF-数字转换器将接收的RF信号转换为DC频带或中频带的数字信号，并且具有可处理所需RF频带信号的动态范围和靠近所需RF频带信号的不需要的信号。 数字预处理器以数字方式控制信号增益，将其发送到调制器/解调器。

公开(公告)号：US20200302279A1

公开(公告)日：2020-09-24

申请号：US16813901

申请日：2020-03-10

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Hyun Kyu YU ,  Young-Su KWON ,  JOO HYUN LEE

IPC: G06N3/063 ,  G11C7/10 ,  G06N3/04

Abstract: An electronic device includes first to n-th cells (‘n’ is an integer of 2 or more) that receive spatial-temporal input signals that indicate an event unit in a time window, a summation circuit that sums first to n-th cell signals recorded in the first to n-th cells for each of first to m-th unit times (‘m’ is an integer of 2 or more) dividing the time window to generate first to m-th summation signals, and an encoding circuit that compares each of the first to m-th summation signals with a threshold value to encode the spatial-temporal input signals into a code of the event unit.