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    TRAINING METHOD AND SYSTEM FOR OPTIMIZATION OF TRAFFIC SIGNAL
    2.
    发明公开
    TRAINING METHOD AND SYSTEM FOR OPTIMIZATION OF TRAFFIC SIGNAL 审中-公开

    公开(公告)号：US20240282194A1

    公开(公告)日：2024-08-22

    申请号：US18529479

    申请日：2023-12-05

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Hun Soon Lee ,  Moonyoung Chung

    IPC: G08G1/081 ,  G06N20/00

    CPC classification number: G08G1/081 ,  G06N20/00

    Abstract: Disclosed is a training method for the optimization of a traffic signal. The method includes segmenting a large-scale road network into intersection groups each including a plurality of intersections, training a reinforcement learning model by allocating a training agent to each intersection group, performing traffic signal control through the inference of an optimal signal based on the trained reinforcement learning model, evaluating whether the results of the execution of the traffic signal control satisfy a preset goal of learning for traffic signal optimization, and repeatedly training the reinforcement learning model based on the results of the evaluation.

    SYSTEM AND METHOD FOR EFFICIENT ADDRESS TRANSLATION OF FLASH MEMORY DEVICE
    3.
    发明申请
    SYSTEM AND METHOD FOR EFFICIENT ADDRESS TRANSLATION OF FLASH MEMORY DEVICE 有权
    用于闪存存储器件的高效地址转换的系统和方法

    公开(公告)号：US20150193339A1

    公开(公告)日：2015-07-09

    申请号：US14204597

    申请日：2014-03-11

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Chang Soo Kim ,  Hun Soon Lee ,  Kyoung Hyun Park ,  Mai Hai Thanh ,  Mi Young Lee ,  Sung Jin Hur

    IPC: G06F12/02 ,  G06F12/10

    CPC classification number: G06F12/0246 ,  G06F12/10 ,  G06F2212/7201

    Abstract: Disclosed are a system and a method for address translation for a flash memory device, and particularly, disclosed is a technology that is capable of efficiently performing address translation between a logical address provided to the outside of a flash memory and a physical address of an actual flash memory in managing the flash memory device. The system includes: a flash memory system writing a corresponding data page by allocating a physical address space when there is a request for writing a data page from storage clients, and performing address translation between a physical address and a logical address; and a logical address space formed between the flash memory system and the storage client to provide the logical address.

    Abstract translation: 公开了一种用于闪速存储器件的地址转换的系统和方法，特别是公开了一种能够在提供给闪存的外部的逻辑地址和实际的闪存的物理地址之间有效地执行地址转换的技术 Flash存储器管理闪存设备。 该系统包括：闪存系统，当存在来自存储客户机的写入数据页的请求时，通过分配物理地址空间，并在物理地址和逻辑地址之间执行地址转换来写入对应的数据页; 以及在闪存系统和存储客户端之间形成的逻辑地址空间以提供逻辑地址。

    Merge join system and method
    4.
    发明授权
    Merge join system and method 有权

    公开(公告)号：US11275741B2

    公开(公告)日：2022-03-15

    申请号：US16193419

    申请日：2018-11-16

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Hun Soon Lee

    IPC: G06F17/00 ,  G06F7/00 ,  G06F16/2455 ,  G06F7/14 ,  G06F16/2458

    Abstract: A merge join method by a merge join system including a database is provided. The merge join system unequally divides data after a current position of a join column participating in merge join in the database into K partitions, K being greater than 2, and compares the first value of each of remaining partitions excluding the first partition from the K partitions with a value to be searched for the merge join, in order to check whether the first value and the value to be searched satisfy a specific condition. Further, the merge join system determines a partition in which the value to be searched is expected to exist based on a comparison result, and applies a k-ary search to the determined partition.

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