知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.05 秒)

    Methods of forming semiconductor devices with extended active regions
    1.
    发明授权
    Methods of forming semiconductor devices with extended active regions 有权
    形成具有扩展活性区域的半导体器件的方法

    公开(公告)号：US07867841B2

    公开(公告)日：2011-01-11

    申请号：US11968242

    申请日：2008-01-02

    申请人： Dong-Chan Lim ,  Byeong-Yun Nam ,  Soo-Ik Jang ,  In-Soo Jung

    发明人： Dong-Chan Lim ,  Byeong-Yun Nam ,  Soo-Ik Jang ,  In-Soo Jung

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/1203

    摘要： A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench. An interlayer dielectric is formed on the semiconductor substrate and the second device isolation layer. A conductive contact is formed extending through the interlayer dielectric layer and directly contacting at least a portion of both the active region and the extension portion of the active region overlying the second device isolation layer.

    摘要翻译： 形成半导体器件的方法可以包括在半导体衬底中形成沟槽以限定有源区。 沟槽填充有第一器件隔离层。 第一器件隔离层的一部分被蚀刻以将第一器件隔离层的顶表面凹陷在半导体衬底的有源区的相邻顶表面下方并且部分地暴露有源区的侧壁。 有源区的暴露的侧壁被外延生长以形成有源区的延伸部分，部分地延伸穿过沟槽中的第一器件隔离层的顶表面。 第二器件隔离层形成在沟槽中凹陷的第一器件隔离层上。 蚀刻第二器件隔离层以暴露有源区的延伸部分的顶表面，并且将第二器件隔离层的一部分留在沟槽的相对侧上的有源区的延伸部分之间。 在半导体衬底和第二器件隔离层上形成层间电介质。 形成延伸穿过层间介电层并且直接接触覆盖在第二器件隔离层上的有源区域和有源区域的延伸部分的至少一部分的导电接触。

    SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS AND METHODS OF FORMING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS AND METHODS OF FORMING THE SAME 有权
    具有扩展活动区域的半导体器件及其形成方法

    公开(公告)号：US20080157262A1

    公开(公告)日：2008-07-03

    申请号：US11968242

    申请日：2008-01-02

    申请人： Dong-Chan Lim ,  Byeong-Yun Nam ,  Soo-Ik Jang ,  In-Soo Jung

    发明人： Dong-Chan Lim ,  Byeong-Yun Nam ,  Soo-Ik Jang ,  In-Soo Jung

    IPC分类号： H01L27/00 ,  H01L21/76

    CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/1203

    摘要： A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench. An interlayer dielectric is formed on the semiconductor substrate and the second device isolation layer. A conductive contact is formed extending through the interlayer dielectric layer and directly contacting at least a portion of both the active region and the extension portion of the active region overlying the second device isolation layer.

    摘要翻译： 形成半导体器件的方法可以包括在半导体衬底中形成沟槽以限定有源区。 沟槽填充有第一器件隔离层。 第一器件隔离层的一部分被蚀刻以将第一器件隔离层的顶表面凹陷在半导体衬底的有源区的相邻顶表面下方并且部分地暴露有源区的侧壁。 有源区的暴露的侧壁被外延生长以形成有源区的延伸部分，部分地延伸穿过沟槽中的第一器件隔离层的顶表面。 第二器件隔离层形成在沟槽中凹陷的第一器件隔离层上。 蚀刻第二器件隔离层以暴露有源区的延伸部分的顶表面，并且将第二器件隔离层的一部分留在沟槽的相对侧上的有源区的延伸部分之间。 在半导体衬底和第二器件隔离层上形成层间电介质。 形成延伸穿过层间介电层并且直接接触覆盖在第二器件隔离层上的有源区域和有源区域的延伸部分的至少一部分的导电接触。

    Methods of forming thin film transistors having lightly-doped drain and source regions therein
    3.
    发明授权
    Methods of forming thin film transistors having lightly-doped drain and source regions therein 失效
    形成其中具有轻掺杂漏极和源极区的薄膜晶体管的方法

    公开(公告)号：US5693546A

    公开(公告)日：1997-12-02

    申请号：US659315

    申请日：1996-06-06

    申请人： Byeong-Yun Nam ,  Sang-Won Lee ,  Jin-Hong Kim

    发明人： Byeong-Yun Nam ,  Sang-Won Lee ,  Jin-Hong Kim

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/265

    CPC分类号： H01L29/66757 ,  H01L29/78621

    摘要： Methods of forming field effect transistors include the steps of forming a composite of layers including an amorphous silicon layer (a--Si), a silicon dioxide layer thereon and a silicon nitride layer on the silicon dioxide layer. A polycrystalline silicon conductive layer is then formed on the silicon nitride layer by depositing and patterning polycrystalline silicon. The polycrystalline silicon conductive layer is then oxidized using thermal oxidation techniques to form an oxide outerlayer. During this step, a portion of the polycrystalline silicon conductive layer will be consumed to define a gate electrode. Dopants of first conductivity type are then implanted into a top surface of the silicon nitride layer, using the oxide outerlayer and the gate electrode as a mask, to form relatively lightly doped preliminary source and drain regions in the amorphous silicon layer. The oxide outerlayer is then removed preferably using a buffered oxide etchant (BOE) solution which does not etch silicon nitride. Following this, dopants of first conductivity type are again implanted into the amorphous silicon layer, using the gate electrode as a mask. The second implantation step causes the formation of a field effect transistor having self-aligned source and drain regions, self-aligned lightly doped source and drain region extensions (LDS, LDD) and a channel region therebetween which has the same length as the gate electrode. By forming the channel region to have the same length as the gate electrode, improved device characteristics can be achieved.

    摘要翻译： 形成场效应晶体管的方法包括以下步骤：在二氧化硅层上形成包括非晶硅层（a-Si），二氧化硅层和氮化硅层的层的复合物。 然后通过沉积和构图多晶硅在氮化硅层上形成多晶硅导电层。 然后使用热氧化技术氧化多晶硅导电层以形成氧化物外层。 在该步骤期间，多晶硅导电层的一部分将被消耗以限定栅电极。 然后，使用氧化物外层和栅电极作为掩模，将第一导电类型的掺杂剂注入到氮化硅层的顶表面中，以在非晶硅层中形成相对轻掺杂的初始源极和漏极区。 然后优选使用不蚀刻氮化硅的缓冲氧化物蚀刻剂（BOE）溶液去除氧化物外层。 接下来，使用栅电极作为掩模，再次将第一导电类型的掺杂剂注入到非晶硅层中。 第二注入步骤导致形成具有自对准的源区和漏区，自对准的轻掺杂源极和漏极延伸（LDS，LDD）的场效应晶体管及其间具有与栅电极相同长度的沟道区 。 通过形成与栅电极具有相同长度的沟道区，可以实现改进的器件特性。

    Method of etching a metal layer using a mask, a metallization method for a semiconductor device, a method of etching a metal layer, and an etching gas
    5.
    发明授权
    Method of etching a metal layer using a mask, a metallization method for a semiconductor device, a method of etching a metal layer, and an etching gas 失效
    使用掩模蚀刻金属层的方法，半导体器件的金属化方法，蚀刻金属层的方法和蚀刻气体

    公开(公告)号：US07226867B2

    公开(公告)日：2007-06-05

    申请号：US10419075

    申请日：2003-04-21

    申请人： Seung-Young Son ,  Cheol-Kyu Lee ,  Chang-Jin Kang ,  Byeong-Yun Nam

    发明人： Seung-Young Son ,  Cheol-Kyu Lee ,  Chang-Jin Kang ,  Byeong-Yun Nam

    IPC分类号： H01L21/302

    CPC分类号： C23F4/00 ,  H01L21/32136 ,  H01L21/32139

    摘要： Methods for etching a metal layer and a metallization method of a semiconductor device using an etching gas that includes Cl2 and N2 are provided. A mask layer is formed on the metal layer, the etching gas is supplied to the metal layer, and the metal layer is etched by the etching gas using the mask layer as an etch mask. The metal layer may be formed of aluminum or an aluminum alloy. Cl2 and N2 may be mixed at a ratio of 1:1 to 1:10. The etching gas may also include additional gases such as inactive gases or gases that include the elements H, O, F, He, or C. In addition, N2 may be supplied at a flow rate of from 45–65% of the total flow rate of the etching gas, which results in a reduction in the occurrence of micro-loading and cone-shaped defects in semiconductor devices.

    摘要翻译： 提供了蚀刻金属层的方法和使用包括Cl 2 N 2和N 2 N的蚀刻气体的半导体器件的金属化方法。 在金属层上形成掩模层，将蚀刻气体供给到金属层，并使用掩模层作为蚀刻掩模，通过蚀刻气体蚀刻金属层。 金属层可以由铝或铝合金形成。 Cl 2 N 2和N 2可以1:1至1:10的比例混合。 蚀刻气体还可以包括另外的气体，例如包括元素H，O，F，He或C的惰性气体或气体。此外，N 2可以以 蚀刻气体总流量的45-65％，这导致半导体器件中的微负载和锥形缺陷的发生减少。

    Methods of forming capacitor structures including L-shaped cavities and related structures
    6.
    发明申请
    Methods of forming capacitor structures including L-shaped cavities and related structures 有权
    形成电容器结构的方法包括L形腔和相关结构

    公开(公告)号：US20050112819A1

    公开(公告)日：2005-05-26

    申请号：US10977385

    申请日：2004-10-29

    申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-II Cho

    发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-II Cho

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

    摘要： Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

    摘要翻译： 形成电容器结构的方法可以包括在衬底上形成绝缘层，在绝缘层上形成第一电容器电极，在第一电容器电极的部分上形成电容器电介质层，以及在电容器电介质层上形成第二电容器电极， 电容器介电层位于第一和第二电容器电极之间。 更具体地，第一电容器电极可以在其中限定空腔，其中腔具有相对于衬底平行的第一部分和相对于衬底垂直的第二部分。 还讨论了相关结构。

    Methods of forming capacitor structures including L-shaped cavities
    8.
    发明授权
    Methods of forming capacitor structures including L-shaped cavities 有权
    形成电容器结构的方法包括L形腔

    公开(公告)号：US07312130B2

    公开(公告)日：2007-12-25

    申请号：US10977385

    申请日：2004-10-29

    申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-Il Cho

    发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-Il Cho

    IPC分类号： H01L21/20

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

    摘要： Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

    摘要翻译： 形成电容器结构的方法可以包括在衬底上形成绝缘层，在绝缘层上形成第一电容器电极，在第一电容器电极的部分上形成电容器电介质层，以及在电容器电介质层上形成第二电容器电极， 电容器介电层位于第一和第二电容器电极之间。 更具体地，第一电容器电极可以在其中限定空腔，其中腔具有相对于衬底平行的第一部分和相对于衬底垂直的第二部分。 还讨论了相关结构。

    Display substrate and method of manufacturing the same
    10.
    发明授权
    Display substrate and method of manufacturing the same 有权
    显示基板及其制造方法

    公开(公告)号：US08835956B2

    公开(公告)日：2014-09-16

    申请号：US13287153

    申请日：2011-11-02

    申请人： Zin-Taek Park ,  Hyeong-Chan Ko ,  Hyun Park ,  Byeong-Yun Nam ,  Sang-Hoon Lee ,  Sung-Hoon Kim

    发明人： Zin-Taek Park ,  Hyeong-Chan Ko ,  Hyun Park ,  Byeong-Yun Nam ,  Sang-Hoon Lee ,  Sung-Hoon Kim

    IPC分类号： H01L33/00 ,  G02F1/1345 ,  H01L27/12

    CPC分类号： H01L27/124 ,  G02F1/13458 ,  H01L27/1288

    摘要： A display substrate includes a substrate, a pixel part, a pad part and a sacrificial electrode. The substrate includes a display area and a peripheral area. The pixel part is on the display area and includes a switching element, and a pixel electrode electrically connected to the switching element. The pad part is on the peripheral area and contacts a terminal of an external device. The pad part includes a pad electrode a contact electrode. The pad electrode includes a first metal layer, and a second metal layer on the first metal layer, and the contact electrode contacts the second metal layer. The sacrificial electrode is spaced apart from the pad electrode and contacts the contact electrode. An exposed portion of the sacrificial electrode is exposed to an external side of the display substrate.

    摘要翻译： 显示基板包括基板，像素部分，焊盘部分和牺牲电极。 基板包括显示区域和周边区域。 像素部分在显示区域上，并且包括开关元件和电连接到开关元件的像素电极。 焊盘部分在外围区域上，并与外部设备的端子接触。 焊盘部分包括焊盘电极和接触电极。 焊盘电极包括第一金属层和第一金属层上的第二金属层，并且接触电极接触第二金属层。 牺牲电极与焊盘电极间隔开并与接触电极接触。 牺牲电极的露出部分暴露于显示基板的外侧。