公开(公告)号：US08046729B1

公开(公告)日：2011-10-25

申请号：US10998101

申请日：2004-11-24

Applicant: Ryan Fung ,  David Galloway

Inventor： Ryan Fung ,  David Galloway

IPC: G06F17/50

CPC classification number: H03K19/173 ,  G06F17/50 ,  G06F17/5031 ,  G06F17/505 ,  G06F2217/62

Abstract: A logic device includes a low-skew network that feeds a subset of elements on the logic device. The low-skew network includes a selector that can select from a plurality of signal sources which includes a first signal source and a second signal source, wherein the second signal source can reach at least one element outside of the subset.

Abstract translation: 逻辑设备包括在逻辑设备上馈送元素的子集的低偏移网络。 低偏移网络包括可以从包括第一信号源和第二信号源的多个信号源中选择的选择器，其中第二信号源可以到达子集外部的至少一个元件。

公开(公告)号：US07694256B1

公开(公告)日：2010-04-06

申请号：US11899097

申请日：2007-09-04

Applicant: David Galloway ,  Ryan Fung

Inventor： David Galloway ,  Ryan Fung

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5054 ,  G06F17/5072 ,  G06F2217/64

Abstract: A method for designing a system on a target device having restricted areas includes determining locations on the target device for all cells in the system by solving one or more equations. Partitioning of cells of a first classification type is performed. One or more equations are modified in response to the partitioning. Revised locations on the target device are determined for the cells by solving the modified one or more equations. The partitioning procedure takes into consideration the classification types of cells as well as restricted areas on the target device.

Abstract translation: 用于在具有受限区域的目标设备上设计系统的方法包括通过求解一个或多个等式来确定目标设备上系统中所有单元的位置。 执行第一分类类型的单元的分区。 响应于分区修改一个或多个等式。 通过求解修正的一个或多个方程，为单元确定目标设备上的修正位置。 分区过程考虑到目标设备上的小区的分类类型以及限制区域。

公开(公告)号：US08402416B1

公开(公告)日：2013-03-19

申请号：US13267334

申请日：2011-10-06

Applicant: Ryan Fung ,  David Galloway

Inventor： Ryan Fung ,  David Galloway

IPC: G06F17/50

CPC classification number: H03K19/173 ,  G06F17/50 ,  G06F17/5031 ,  G06F17/505 ,  G06F2217/62

Abstract: A logic device includes a low-skew network that feeds a subset of elements on the logic device. The low-skew network includes a selector that can select from a plurality of signal sources which includes a first signal source and a second signal source, wherein the second signal source can reach at least one element outside of the subset.

Abstract translation: 逻辑设备包括在逻辑设备上馈送元素的子集的低偏移网络。 低偏移网络包括可以从包括第一信号源和第二信号源的多个信号源中选择的选择器，其中第二信号源可以到达子集外部的至少一个元件。

公开(公告)号：US07788614B1

公开(公告)日：2010-08-31

申请号：US11899127

申请日：2007-09-04

Applicant: David Galloway ,  Ryan Fung

Inventor： David Galloway ,  Ryan Fung

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method for designing a system on a target device having restricted areas includes determining locations on the target device for all cells in the system by solving one or more equations. The one or more equations are modified, or supplemented by adding one or more additional equations, by applying spreading forces to the cells that take into consideration classification types of the cells and restricted areas on the target device that do not support the classification types. Revised locations on the target device are determined for the cells by solving the modified one or more equations.

Abstract translation: 用于在具有受限区域的目标设备上设计系统的方法包括通过求解一个或多个等式来确定目标设备上系统中所有单元的位置。 通过对考虑到不支持分类类型的单元格和目标设备上的限制区域的分类类型对单元格应用展开力，通过添加一个或多个附加方程来修改或补充一个或多个等式。 通过求解修正的一个或多个方程，为单元确定目标设备上的修正位置。

公开(公告)号：US08898609B1

公开(公告)日：2014-11-25

申请号：US11488392

申请日：2006-07-18

Applicant: Vadim Gouterman ,  Ryan Fung

Inventor： Vadim Gouterman ,  Ryan Fung

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/84

Abstract: A method for performing routing for a logic design includes utilizing signal transition time as a criteria for selecting resources to provide interconnection between the components of the logic design.

Abstract translation: 用于执行逻辑设计的路由的方法包括利用信号转换时间作为选择资源以提供逻辑设计的组件之间的互连的准则。

公开(公告)号：US08232826B1

公开(公告)日：2012-07-31

申请号：US12692847

申请日：2010-01-25

Applicant: Andy Nguyen ,  Ling Yu ,  Ryan Fung

Inventor： Andy Nguyen ,  Ling Yu ,  Ryan Fung

IPC: H03H11/26

CPC classification number: H03K17/005

Abstract: A circuit with N primary outputs and a delay chain with M selection multiplexers. M can be less than N, and M is based on the number of primary outputs that simultaneously require a delayed signal from the delay chain. The N primary outputs may include core outputs and/or registers. Each of the M selection multiplexers feed directly or indirectly a subset of the N primary outputs.

Abstract translation: 具有N个主输出的电路和具有M个选择多路复用器的延迟链。 M可以小于N，M基于同时需要来自延迟链的延迟信号的主输出的数量。 N个主输出可以包括核心输出和/或寄存器。 每个M选择多路复用器直接或间接馈送N个主输出的子集。

公开(公告)号：US20110299346A1

公开(公告)日：2011-12-08

申请号：US12793583

申请日：2010-06-03

Applicant: Ryan Fung ,  Joshua David Fender

Inventor： Ryan Fung ,  Joshua David Fender

IPC: G11C7/00 ,  H03K19/00

CPC classification number: G11C7/222 ,  G11C7/1036 ,  G11C7/1078 ,  G11C7/1093

Abstract: An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.

Abstract translation: 一种装置包括耦合到电子装置的接口电路。 接口电路使用选通信号提供与电子设备的源同步通信。 接口电路被配置为对选通信号进行门控，以便与电子设备成功通信。

公开(公告)号：US07676768B1

公开(公告)日：2010-03-09

申请号：US11437950

申请日：2006-05-19

Applicant: Mark Bourgeault ,  Ryan Fung ,  David Lewis

Inventor： Mark Bourgeault ,  Ryan Fung ,  David Lewis

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/00323 ,  H03K19/17736

Abstract: An electronic design automation (EDA) tool alters a user's netlist to provide timing success for distribution of asynchronous signals. Distribution networks are used with the addition of pipeline registers before and/or after the distribution buffer. Or, a tree of pipeline registers is inserted between the asynchronous source and the destination registers. Or, any number of distribution networks are stitched together and pipeline stages may be inserted before and/or after each distribution buffer. Or, beneficial skew is utilized by introducing a delay component that skews a clock signal. The skewed clock signal drives a pipeline register that is inserted before a distribution buffer in order to improve timing margin. Any of various compilation techniques may be used within the EDA tool to solve the problem of distributing high-speed, high-fanout asynchronous signals. The technique has utility for high-performance FPGAs and structured ASIC families, as well as for low-cost FPGAs and other types of logic devices.

Abstract translation: 电子设计自动化（EDA）工具改变用户的网表以提供异步信号分配的时序成功。 分配网络在分配缓冲区之前和/或之后添加流水线寄存器时使用。 或者，在异步源和目标寄存器之间插入一条流水线寄存器树。 或者，任何数量的分发网络被缝合在一起，并且可以在每个分发缓冲器之前和/或之后插入流水线阶段。 或者，通过引入偏移时钟信号的延迟分量来利用有益的偏移。 偏斜时钟信号驱动在分配缓冲器之前插入的流水线寄存器，以便提高定时裕度。 可以在EDA工具中使用各种编译技术中的任何一种来解决分配高速，高扇出异步信号的问题。 该技术可用于高性能FPGA和结构化ASIC系列，以及低成本FPGA和其他类型的逻辑器件。

公开(公告)号：US07370291B2

公开(公告)日：2008-05-06

申请号：US11069887

申请日：2005-02-28

Applicant: Ryan Fung ,  Ketan Padalia

Inventor： Ryan Fung ,  Ketan Padalia

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A method is provided for mapping logic design memory into physical memory devices of a programmable logic device. User constraints and physical constraints may be taken into account in generating the mapping solution. Functional block layout on the programmable logic device may be taken into account when generating the mapping solution. Multiple types of physical memory types may be considered and logic design memory may be mapped to those types of physical memory devices that are determined to be the most appropriate. A mapping solution may be optimized using, for example, simulated annealing.

Abstract translation: 提供了一种用于将逻辑设计存储器映射到可编程逻辑器件的物理存储器件中的方法。 在生成映射解决方案时可以考虑用户约束和物理约束。 在生成映射解决方案时，可以考虑可编程逻辑器件上的功能块布局。 可以考虑多种类型的物理存储器类型，并且可以将逻辑设计存储器映射到被确定为最合适的那些类型的物理存储器设备。 可以使用例如模拟退火来优化映射解决方案。

公开(公告)号：US07308664B1

公开(公告)日：2007-12-11

申请号：US10774857

申请日：2004-02-09

Applicant: Ryan Fung ,  Vaughn Betz ,  William Chow

Inventor： Ryan Fung ,  Vaughn Betz ,  William Chow

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5077 ,  G06F2217/84

Abstract: A method for designing a system includes determining minimum and maximum delay budgets for connections. Routing resources are selected for connections in response to the minimum and maximum delay budgets.

Abstract translation: 一种用于设计系统的方法包括确定连接的最小和最大延迟预算。 选择路由资源用于响应最小和最大延迟预算的连接。