Abstract:
A circuit with N primary outputs and a delay chain with M selection multiplexers. M can be less than N, and M is based on the number of primary outputs that simultaneously require a delayed signal from the delay chain. The N primary outputs may include core outputs and/or registers. Each of the M selection multiplexers feed directly or indirectly a subset of the N primary outputs.
Abstract:
A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator.
Abstract:
A circuit includes a comparator, a resistor divider, a control circuit, a multiplexer, and a programmable gain amplifier. The comparator is operable to measure an internal voltage of the circuit based on a selected reference voltage. The resistor divider is operable to generate reference voltages. The control circuit is operable to generate a select signal based on an output signal of the comparator. The multiplexer is operable to select one of the reference voltages from the resistor divider as the selected reference voltage based on the select signal. The programmable gain amplifier is configurable to generate a compensation voltage to compensate for an offset voltage of the comparator. The compensation voltage is provided to an input of the comparator.
Abstract:
A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit receives an output signal of the comparator and generates a select signal. The multiplexer transmits one of the reference voltages from the resistor divider to the comparator as the selected reference voltage in response to the select signal.
Abstract:
A circuit includes a comparator, a resistor divider, a control circuit, a multiplexer, and a programmable gain amplifier. The comparator is operable to measure an internal voltage of the circuit based on a selected reference voltage. The resistor divider is operable to generate reference voltages. The control circuit is operable to generate a select signal based on an output signal of the comparator. The multiplexer is operable to select one of the reference voltages from the resistor divider as the selected reference voltage based on the select signal. The programmable gain amplifier is configurable to generate a compensation voltage to compensate for an offset voltage of the comparator. The compensation voltage is provided to an input of the comparator.
Abstract:
A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit receives an output signal of the comparator and generates a select signal. The multiplexer transmits one of the reference voltages from the resistor divider to the comparator as the selected reference voltage in response to the select signal.
Abstract:
A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator.
Abstract:
Arrays of memory elements may have data lines and address lines. Each memory element may have five transistors. An address decoder may receive an undecoded address signal and may produce a corresponding decoded address signal. The decoded version of the address signal may be used in addressing the memory elements in the memory array. The memory array may be loaded with configuration data. Loaded memory elements may each provide a static output control signal that configures a programmable logic transistor in programmable logic. The memory elements may be powered with an elevated voltage during normal operation. Boosted address signals may be used when addressing the memory array. The address decoder may contain circuitry that is responsive to a clear control signal and an address output enable signal. The memory element array may be cleared by asserting the clear control signal and address output enable signal.
Abstract:
Rather than have a unique code set per TV product, a common code base is provided to service multiple products and even multiple product lines. Embedded systems can be upgraded through a network connection. The software architecture provides a flexible approach to supporting multiple product offerings through a plug-in modular middle-ware and to providing standardized hardware acceleration for both 2D and 3D graphics. The plug-in capability provides for feature additions and upgrades after sale.
Abstract:
A method consistent with certain implementations involves switching one or more loudspeakers to behave as one or more microphones while remaining loudspeakers behave as speakers. An audible signal is generated and the outputs of the microphones are processed to identify geometric location of loudspeakers. A filter transfer function is generated for the loudspeakers to psycho-acoustically relocate one or more of the loudspeakers from the identified geometric locations when the one or more loudspeakers are used as loudspeakers. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.